Test
Ch 9 True/False
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Preguntas del test (13)
1A relocation register is used to check for invalid memory addresses generated by a CPU.
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2Reentrant code cannot be shared.
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3There is a 1:1 correspondence between the number of entries in the TLB and the number of entries in the page table.
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4Hierarchical page tables are appropriate for 64-bit architectures.
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5The ARM architecture uses both single-level and two-level paging.
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6Fragmentation does not occur in a paging system.
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7Hashed page tables are particularly useful for processes with sparse address spaces.
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8Inverted page tables require each process to have its own page table.
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9Without a mechanism such as an address-space identifier, the TLB must be flushed during a context switch.
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10A 32-bit logical address with 8 KB page size will have 1,000,000 entries in a conventional page table.
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11Hashed page tables are commonly used when handling addresses larger than 32 bits.
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12The x86-64 bit architecture only uses 48 of the 64 possible bits for representing virtual address space.
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13Mobile operating systems typically support swapping.
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Información
- Descripción
- Computer Science Test sobre Ch 9 True/False, creado por Storm Davis el 26/04/2019.
- Autor
- Storm Davis
- Idioma
- English
- Visitas
- 7
- Historial
- Creado el 26 abr 2019 · actualizado el 26 abr 2019
- Etiquetas
- Valoración
- Aún sin valoraciones Valora este test