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Giovanna Benetti Computing Physics Inglés 9 fichas

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  1. 1Central Processing Unit (CPU)- Processor
    - Main Memory
    - Address, Control and Data Bus
    - Input/Output (I/O) Controllers
  2. 2Control BusUsed to send control signals between each I/O controller and the processor, as well as between the processor and memory
  3. 3Control Bus Signals- Memory Read - causes data from the addressed location to be placed on the data bus
    - Memory Write - causes data on the data bus to be written into the addressed location
    - Bus Request – indicates that a device is requesting use of the data bus
    -Bus Grant – indicates that the CPU has granted access to the data bus
    -Clock – used to synchronize operations
    -Reset – initializes all requests
  4. 4Data Bus-Sends data between CPU components
    -Is bi-directional
    The width of the data bus is defined by the number of wires or lines it contains
    -Bus width affects overall system performance
  5. 5Address Bus-Sends memory addresses from the processor to the CPU components
    -The width of the address bus determines the maximum possible memory addresses of the system
  6. 6WordsMemory is divided up in equal units called words -- each word has a separate memory address; word length is usually 8, 16, 32 or 64 bits
  7. 7Stored Program ConceptMachine code instructions are loaded into main memory to be executed by the processor.
    The instructions are fetched one at a time and executed immediately by the processor in a sequential order
  8. 8John von Neumann ArchitectureInstructions and data are stored in a common main memory and transferred using a single shared bus
    -Owing primarily to cost and programming complexity, almost all general purpose computers are based on von Neumann's principles
    John von Neumann Architecture
  9. 9Harvard ArchitectureAn alternative model separates the data and instructions into separate memories using different buses
    -Harvard principles are usually used with specialist embedded systems such as digital signal processing where speed takes priority over complexity of design
    -Can be faster than von Neumann architecture because data and instructions can be fetched in parallel instead of competing for the same bus
    Harvard Architecture

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Physics Computing Fichas sobre Sin título, creado por Giovanna Benetti el 13/02/2020.
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Giovanna Benetti · feb 2020
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13 feb 2020
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