Flashcards
Digital Timing
Cards in this deck (9)
- 1Propagation Delay (T_pd)longest delay of the circuit
T_pd <= Tc - (T_pcq + T_setup)
T_pd <= Tc - (T_pcq + T_setup + T_skew )
T_c: controlled by project
T setup and T_pcq are determined by manufacturer
We can only control T_pd
- 2Contamination Delay (T_cd)shortest delay of the circuit
T_cd >= T_hold - T_ccq
T_ccq and T_hold are determined by the manufacturer
usually, flops are designed so T_hold =0, or that T_hold < T_ccq
can only fix hold timing violations by increasing the contamination delay in the logic (T_cd) aka add buffers to the shortest path
- 3Setup Time (T_setup)Time the input is required to be stable before the clock edge
- 4Hold Time (T_Hold)Time that the input is required to be stable after the clock edge
T_hold <= T_ccq + T_cd
- 5Clock to Q Contamination Delay (T_ccq)time between clock edge and output changing
- 6Clock to Q Propagation Delay (T_pcq)time between clock edge and when output finishes changing
- 7Clock Period (T_c)T_c >= T_pcq + T_pd + T_setup
T_c >= T_pcq + T_pd + T_setup + T_skew - 8Skew for Hold TimeT_skew + T_hold <= T_ccq + T_cd
Tcd >= T_hold + T_skew - T_ccq
sometimes we have a large T_ccq in order to reduce skew (if it is there)
- 9MetastabilityA flip flop enters into meta-stable state, when the hold or setup window is violated. At this time, the output of flip flop is unpredictable.
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- Flashcards on Digital Timing, created by Kai Kaneshina on 01/02/2019.
- Created by
- Kai Kaneshina · Feb 2019
- Updated
- Feb 1, 2019
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