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Eljin Aguilar Microprocessors hard English 52 cards

01Handout01

Cards in this deck (52)

  1. 1It has the capability of executing instructions at an extremely high speed.microprocessor
  2. 2five basic components of microprocessorsarithmetic logic unit (ALU),
    control unit (CU),
    registers,
    buses,
    and timing unit
  3. 3Instruction Set Architecture Classifications• Complexity-Based Classification
    • Instruction Operand-Based Classification
  4. 4Measure based on the complexity of instructions)Complexity-Based Classification
  5. 5• Complexity-Based Classification so Complex instruction set computers (CISC)
    o Reduced Instruction Set Computers (RISC)
  6. 6 One of the advantages of this architecture is performing multiple operations in a single complex instruction. However, complex instructions require many processor clock cycles to complete, wherein most of the instructions can access the memory.o Complex instruction set computers (CISC)
  7. 7 This architecture is suited for those scenarios wherein the processor speed-matches memories. This speed-matching reduces the penalty for instruction or parameter fetching from the memory.o Reduced Instruction Set Computers (RISC)
  8. 8• Instruction Operand-Based Classificationso Memory-memory
    o Register-memory
    o Register-register
  9. 9This type of ISA allows more than one operand of most instructions to be specified in memory.o Memory-memory
  10. 10This allows one operand of an instruction to be specified in memory, while the other operand is in the CPU register.o Register-memory:
  11. 11This is also called load-store architecture. Direct access to the memory is not allowed to most of the instructions in this ISA.o Register-register:
  12. 12Memory Interface-Based Architecturesvon Neumann architecture
    Harvard architecture
  13. 13it uses a common bus for both data as well as code memory. As a result, either an instruction can be fetched from memory, or data can be read from or written to the memory during each memory access cycle.von Neumann architecture
  14. 14it utilizes separate buses for accessing code and data memories. Using separate buses for code and data memories allows instructions and data to be accessed simultaneously.Harvard architecture
  15. 15Software Sub-Systems• Operating System (OS)
    • Device drives or drivers
    • Libraries
    • Applications
  16. 16o It is in-charge of a collection of resources, including the microprocessor, memory, I/O devices. o It manages these resources using the hardware architecture-dependent OS components.• Operating System (OS)
  17. 17It allows the operating system to communicate with the hardware devices.• Device drives or drivers
  18. 18This is a collection of function calls developed for a specific job and is made available to the user.• Libraries
  19. 19It is a collection of one or more programs designed to perform operations for a specific application requirement.• Applications
  20. 20These are used to convert the user programs to executables, which can be interpreted and run by the microprocessor.Software Development Tools
  21. 21o If the user program is written in assembly language, the use of an assembler is needed to convert it to a machine code. o Assembly language programs are also called low-level programs. o If the user program is written in a high-level language, the compiler converts it to the machine code. o The process of converting a user program to machine code using either a compiler or an assembler.• Compilation Process
  22. 22o The job of a __ is to construct an executable by combining different object codes obtained after compiling the user program codes or files.linker
  23. 23The use of libraries at the time of building an executable is called __static linking.
  24. 24 Libraries that are not used at the time of building an executable, but are used during the execution at runtime, are called ____dynamic link libraries (DLL).
  25. 25Software-Only Methods• Software Simulators
    • Monitors
  26. 26It is a program running on an independent computer hardware platform. It can simulate the execution of the instruction set and the behavior of an I/O of the target microcontroller.• Software Simulators –
  27. 27It is usually residing at the top or bottom region of the microcontroller's memory. It can be used to download to burn the program code in the microcontroller, execute the code, set breakpoints, visualize and modify memory contents or registers.• Monitors
  28. 28Software-Hardware Debugging Tools• Burn and Learn
    • In-Circuit Emulators (ICE)
    • In-Circuit Debuggers (ICD)
  29. 29In many non-complex embedded system developments, the conventional method can be used for debugging purposes. o Write or modify the program code. __ the executable code to the microcontroller chip using a programmer or in-circuit programming capability. Run the program (reset) and learn (observe) for proper functioning.• Burn and Learn
  30. 30It is a small hardware tool connected to the targeted microcontroller for in-depth debugging.• In-Circuit Emulators (ICE
  31. 31It is a small hardware tool that debugs the targeted microcontroller in Realtime.• In-Circuit Debuggers (ICD)
  32. 32• It is a common pathway through which information flows from one computer component to another.bus
  33. 33• Data bus typeso Parallel bus
    o Serial bus
  34. 34It carries data from one component to another. It is unidirectional for input and output devices and bi-directional for memory and CPU. It is typically a group of wires that connects different components of the computer internally or externally.• Data bus
  35. 35transfers several data bits at the same. These buses typically have 8, 16, 32, or 64 data lines. Ex: ISA, PCI, VESA, and EISA.o Parallel bus
  36. 36uses the same line to transfer different data bits of the same byte/word. Typically, they have only one data line with bits being sent one after the other. Ex: USB and IEEE 1394.o Serial bus
  37. 37• Control bus typeso Bus protocols
     Synchronous Buses
     Asynchronous Buses
    o Bus Aarbitration
  38. 38need to be established for data communication to flow correctly. It may involve characteristics such as the width of the data bus, data transfer size, bus protocols, clocking, etc.o Bus protocols
  39. 39In this bus, its operations are synchronized regarding a clock signal. The bus clock is generally derived from the computer system clock; however, it is often slower than the master clock. Synchronous Buses
  40. 40These buses have no system clock. The process of handshaking is done to properly conduct the transmission of data between the sender and the receiver. Asynchronous Buses
  41. 41o Bus Arbitration types Centralized Arbitration
    • Daisy Chaining
    • Polling Method
    • Independent Request
     Distributed Arbitration
  42. 42A device that initiates data transfers on the bus at any given time is called a bus master. In a computer system, there may be more than one bus master, such as a DMA controller or a processor. These devices share the system bus. When the current bus master relinquishes, another bus can acquire the control of the processor.o Bus Arbitration
  43. 43Only a single hardware device controls the required arbitration, either a processor or an arbiter. Centralized Arbitration
  44. 44It is a simple and cheaper method where all the masters use the same line for making bus requests.• Daisy Chaining
  45. 45In this method, the controller is used to generate address lines for the master.• Polling Method
  46. 46In this scheme, each bus has its bus request and a grant. The built-in priority decoder selects the highest priority requests and asserts the system.• Independent Request
  47. 47Each module may claim the bus. All modules have their control logic to manage present buses. Distributed Arbitration
  48. 48It carries a memory address o It is used (by the CPU or the DMA-enabled device (direct memory access) to locate the physical address and to communicate read/write commands. o All address busses are read and written by the CPU or DMA in the form of bits.  Ex: A system with a 32-bit address bus can address 4 gibibytes of memory space.• Address bus
  49. 49. A ___ is a numerical value used for identifying a memory location.memory address
  50. 50It is a logic used in electronic circuits wherein a third state, the high-impedance state (Hi-Z), is added to the original Logic 1 and Logic 0 statesTristate Logic
  51. 51• Aside from the two (2) terminals (namely A and Z), the third terminal (Enable) acts as a selector that blocks out circuits that are not being used. • It can be thought of as an input- controlled switch with an output that can be electronically turned “ON” or “OFF” through an external “Control” or “Enable” ( EN ) signal input.• Aside from the two (2) terminals (namely A and Z), the third terminal (Enable) acts as a selector that blocks out circuits that are not...
  52. 52Characteristics of a Tristate Logic in Computer BusesTristate Logic is used to allow multiple circuits to share the same output or bus lines, which may not be capable of listening to more than one device or circuit at a time.
    • The processor controls which device has access to the bus by setting the address on the address bus.
    • Only one tristate device can use the bus at any time.
    • The devices not using the bus are disconnected. Their outputs are set to have a high impedance (Hi-Z).
    • Tristate devices respond to a unique address on the address bus.
    • When the main tristate device is disconnected, other devices can share/use the same data bus line.

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hard Microprocessors Flashcards on 01Handout01, created by Eljin Aguilar on 17/02/2025.
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Eljin Aguilar
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