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01Handout01

Eljin Aguilar Intro to HDL normal English 41 cards

Cards in this deck (41)

  1. 1is a set of notations, similar to software programming languages, used for modeling the logical function of digital circuits and systems.Hardware Description Language
  2. 2• HDLs allow you to describe a circuit using words and symbols and then develop software that can convert that textual description into configuration data loaded into such as FPGAs and othersProgrammable
    Logic Devices (PLDs)
  3. 3is an integrated circuit designed to be configured as "field-programmable" by a customer or a designer after manufacturing.Field-programmable gate array (FPGA)
  4. 4(Programmable pins)IOB – Input/Output Block
  5. 5(Programmable Gates)CLB – Configuration Logic Block
  6. 6Statements in HDL code involves __parallel operation,
  7. 7programming languages represent __sequential operation.
  8. 8the processor will execute lines of code one at a time, following the top-to-bottom organization that we use when reading text on a page.programming languages,
  9. 9we are describing digital hardware, and separate portions of this hardware can operate simultaneously, although the corresponding lines of code are written using a top-to-bottom organization.In HDL code
  10. 10is an important concept in engineering design that allows us to specify how systems will operate without getting overburdened with specific implementation details.Abstraction
  11. 11At this level, the behavior of a system is described by stating a set of broad specifications.System Level
  12. 12At this level, the specifications begin to be broken down into sub-systems, each with an associated behavior that will accomplish a part of the primary task.Algorithmic Level
  13. 13At this level, the details of how data is moved between and within sub-systems are described. Also, data is manipulated based on system inputs.Register Transfer Level
  14. 14At this level, the design is described using basic gates and registers (or storage elements). The gate-level is essentially a schematic (either graphically or text-based) that contains the components and connections that will implement the functionality from the above levels of abstraction.Gate level
  15. 15This level describes the operation of the basic gates and registers using transistors, wires, and other electrical components such as resistors and capacitors.Circuit Level
  16. 16This level describes how different materials are combined and shaped to implement the transistors, devices, and wires from the circuit level.Material Level
  17. 17Digital Design Flow1. Specifications
    2. Functional Design
    3. Synthesis
    5. Place and Route
    6. Verification
    7. Fabrication
  18. 18It refers to the description of the desired behavior of the circuit. State the desired behavior of the design using broad, high-level specifications.1. Specifications
  19. 19Describe the high-level architecture of the design (e.g., block diagrams for inputs/outputs, sub- systems) and behavior (truth tables, state diagrams, and/or algorithms).2. Functional Design
  20. 20Create the gate-level connection (schematic or netlist) of the design using the logic synthesis process (KMAPS or automated CAD tools).3. Synthesis
  21. 21Select the logic technology that will achieve the specifications (CMOS ASIC). Manipulate the gate-level schematic into a form that is suitable for this technology.4. Technology Mapping
  22. 22Arrangement of the components to minimize the area needed (board or chip) and wire all connections to minimize interconnection length and crossings.5. Place and Route
  23. 23Once a technology is chosen and the routing is complete, the gate and wiring delays can be used to estimate whether the final design meets the timing and power consumption requirements of the original specifications.6. Verification
  24. 24Once the design is verified, it can be implemented. (ASIC, programmable device, board-level, discrete parts)7. Fabrication
  25. 25is the interpretation of the HDL statements to produce human-readable output, such as timing diagrams. It predicts approximately how the hardware will behave before it is fabricated.Simulation
  26. 26is the compilation of high-level behavioral and structural HDL statements into a flattened gate- level connection (netlist), which can then be used directly either to layout a printed circuit board, to fabricate a custom integrated circuit, or to program a programmable logic device (PLDs).Synthesis
  27. 27This modeling is used to implement the lowest-level modules in which it is involved gates in relation to the HDL code.Gate Level Modeling
  28. 28Common Hardware Description Languages• Verilog
    • VHDL (Very High-Speed Integrated Circuits Hardware Description Language or VHSIC HDL)
    • System Verilog
  29. 29was developed by Gateway Design Automation as a proprietary language for logic simulation in 1984. It became an IEEE standard in 1995 and was updated in 2001 [IEEE 1364-01].• Verilog
  30. 30was originally developed in 1981 by the Department of Defense to describe the structure and function of hardware. The IEEE standardized VHDL in 1987 and updated the standard several times since [IEEE 1076-08].• VHDL (Very High-Speed Integrated Circuits Hardware Description Language or VHSIC HDL)
  31. 31was introduced in 2005 [IEEE 1800-2009], which streamlines many of the annoyances of Verilog and adds high-level programming language features. It was developed to provide an evolutionary path from VHDL and Verilog to support the complexities of System-on-Chip (SoC) designs, which takes an object-oriented programming approach.• SystemVerilog
  32. 32Basic HDL concepts• Timing
    • Concurrency
    • Hardware Simulation
    • Signal Update
  33. 33Timingo Inertial Delay
    o Transport Delay
  34. 34swallow pulses much narrower than the delay amount.Inertial Delay
  35. 35let all pulses pass through irrespective of their width.Transport Delay
  36. 36o In at this system, many process signals can happen at the same time. o In efficiency handling, only one process at a time can be accessed. o Therefore, there is a need to ‘control’ the passage of time to a specific flow of signals.Concurrency
  37. 37• Hardware Simulationo Analysis
    o Elaboration
    o Simulation
  38. 38Syntax of hardware description is checked and interpreted.Analysis
  39. 39This is a preparatory step that sets up a hierarchically described circuit for simulation.Elaboration
  40. 40Event-driven simulation is carried out.Simulation
  41. 41• - maintains a time-ordered queue of signals which are waiting to acquire their assigned values. o All signals waiting for acquiring their values at this time are updated. o If this updating results in a change in the value of a signal, an Event is said to have occurred on this signal.Signal Update

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normal Intro to HDL Flashcards on 01Handout01, created by Eljin Aguilar on 18/02/2025.
Created by
Eljin Aguilar · Feb 2025
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Feb 19, 2025
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