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Eljin Aguilar Intro to HDL normal English 34 cards

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1is designed by using some IC. The input to any digital circuit is in binary form. These circuits can be represented either in a combinational way or a sequential way.digital circuit
2is a digital circuit whose output depends only on the current inputs. • The circuit has no memory or feedback loops.Combinational logic
3are circuits that can select one of many values based on the selection input. • In the figure, the multiplexer will select one of the six inputs, a through f, and output it on g. • The ‘sel’ input, in this case, needs to be one-hot. • A one-hot signal has exactly one bit that is 1.Multiplexers
4It converts a binary (encoded) value into a one- hot representation. They are commonly drawn in a box with a label specifying that it is a decoder.decoder
5are the opposite of decoders. They convert a one-hot value into a binary representation.Encoders
6it takes a set of inputs and then outputs a one- or-none-hot value. • The bit that is 1 in the output will be the most significant bit in the input that is 1. • Each input has priority over the bits lower than it (the MSB has the highest priority).arbiter
7is a type of circuit whose output depends the current inputs and the sequence of previous inputs.Sequential logic
8asynchronous circuits that change state immediately when enabled.• Event-Driven
9synchronous circuits that are synchronized to a specific clock signal.• Clock Driven
10a combination of the two that responds to triggering pulses.• Pulse Driven
11is a signal that toggles between 0 and 1 with a set frequency. The important parts of the clock signal are the edges.clock
12occur when the clock transitions from 0 to 1.Rising edges
13occur when the clock transitions from 1 to 0 and are used less often.Falling edges
14Sequential Logic CircuitsFeedback Loop.
Latches
Flip-flop
Counters
15The two inverters or NOT gates are connected in series, with the output at Q fed back to the input. This configuration never changes state because the output will always be the same and it is permanently set.Feedback Loop.
16are basic storage elements that operate with signal levels (rather than signal transitions). Latches are controlled by clock transition flip-flops. Latches are level-sensitive devices.Latches
17is a circuit that maintains a state until directed by input to change the state. A basic flip-flop can be constructed using four-NAND or four-NOR gates.Flip-flop
18are used in digital electronics for counting purposes. They can count specific events happening in the circuit. They can also be designed with the help of flip flops.Counters
19is a Hardware Description Language in which is in a textual format for describing electronic circuits and systems. It is intended to be used for verification through simulation, timing analysis, test analysis, and logic synthesis. It supports many levels of abstraction such as:Verilog
20Verilog Abstractions• Behavioral level
• Register-transfer level
• Gate level
21o This level describes a system by concurrent algorithms (Behavioral). Every algorithm is sequential, which means it consists of a set of instructions that are executed one by one. Functions, tasks, and blocks are the main elements.• Behavioral level
22o Designs using this level specify the characteristics of a circuit using operations and the transfer of data between the registers.• Register-transfer level
23o Within this level, the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (basic gates).• Gate level
24consists of one or more characters and every single character. Verilog lexical tokens are case sensitive and all of its keywords are in lowercase.token
25– It can contain characters for spaces, tabs, new-lines, and form feeds. o These characters are ignored except when they serve to separate tokens. o White space characters are Blank space, Tabs, Carriage returns, Newline, and Form feeds.• White Space
26comments begin with the token “//” and end with a carriage return. (double forward slash)o Single line
27begin with the token “/*” and end with the token “*/”. (forward slash and asterisks)o Multiline comments
28A value either in binary, octal, decimal, or hexadecimal format. o Either in integers, real, signed, or unsigned numbers. o The syntax is given by − o Size or unsized number can be defined in and defines whether it is binary, octal, hexadecimal, or decimal.• Numbers
29It is the name used to define the object, such as a function, module, or register. o Identifiers should begin with alphabetical characters or underscore characters. o Ex: A - Z , a - z , _ . o Identifiers are a combination of alphabetic, numeric, underscore and $ characters. They can be up to 1024 characters long.• Identifiers
30These are special characters used to put conditions or to operate the variables.• Operators
31Words that have special meaning in Verilog. o It includes compiler directives and system tasks and functions. o Ex: assign, case, while, wire, reg, and, or, nand, and module. Note: They should not be used as identifiers.• Keywords
32The basic logic gates using one output and many inputs are used in Verilog. It uses one of the keywords - and, nand, or, nor, xor, xnor for use in Verilog for N number of inputs and 1 output.Gate Primitives
33These primitives include both buffers and inverters. o They have a single input and one or more outputs. It stands for either the keyword buf or not gate.Transmission Gate Primitives
34not –__ buf – __ bufif0- __enable. bufif1 – ___ notif0 – ___ notif1 – ____not – n output inverter.
buf – n output buffer.
bufif0 – tristate buffer, active low enable. bufif1 – tristate buffer, active high enable. notif0 – tristate inverter, active low enable. notif1 – tristate inverter, active high enable

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Description: normal Intro to HDL Flashcards on 02Handout01, created by Eljin Aguilar on 19/02/2025.
Created by: Eljin Aguilar
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