Flashcards
Pipeline
Cards in this deck (15)
- 1Purpose of pipelineWe want all parts of the processor for different instructions at the same time
- 2why pipeline?-If we keep the pipeline full we getter throughput (per time)
- Does not reduce the execution time of an individual instruction. In fact, it usually slightly increases the execution time of each instruction due to overhead in the pipeline control. - 3Ideally we get N*x speedup for a pipe with N stages - why not a zillion stages?- Most things cant be broken into small so small chunks
-overhead for every stage - we need to store the stage to keep track - 4What is the speedup for 10 pipeline stages?ca 10 x faster (for example: we will produce a car every 4/10 hours which is 10x faster than 4 hours with pipelined version. (Still takes 4 hours PER CAR)
- 5A none-pipe instruction takes 120 ns. If the instruction is pipelined with 10 stages and pipeline reg take 6 ns, what is the overhead?each stage: 120/10 = 12ns. Between them we have reg of 6ns -> 1 calculation every 18 ns. The ration is: 6/18ns=33%
- 6What are the five stages of pipelining?IF - instruction fetch, register read
ID - instruction decode
EX: execute operation
MEM: access mem
WB: write result back to reg - 7Speedup of pipelineTime per finished non-pipeline
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Time per finished pipelined + Time spent in registers - 8Data hazardWhen a pipeline must be stalled because one step must wait for another to complete.
- 9What is the speedup obtained from pipelining?time per instruction (no pipe) / time per instruction (with pipe )+ regtime
- 10Write the five stages of pipelining that we use when writing diagrams (workshop t.ex.)im - instruction memory Fetch instruction from memory
rf - register file Decode instruction and register read
alu - Execute operation / calculate address
dm - data memory Access memory
rf - register file Write result back to register - 11The pipeline allows us to run faster by1. Increase clock frequency (shorter chunks of work)
2. Process different parts of different instruction in parallel
3. Ideally n× speedup for n-stage pipeline - 12Time per finished unit pipelined =Time per finished unit non-pipeline
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Number of pipeline stages - 13What are branch delay slots?The instructions (normally 1) that always executes after a branch even if they
don’t belong to the chosen branch. - 14How can we speed up the branch process?Branch resolving can be made faster by adding new wires / hardware, down to 1 cycle, so new
instructions can begin after first RF. - 15A processor takes 180 ns for the longest instruction. We pipeline with 6 stages with 6 registers that take 10ns. How much time does it take for one instruction compared to the un-piped version?The only thing that changes in time/instruction is the register time -> 6*10 = 60 ns LONGER! We still have the same latency, but faster throughput
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- Dark Flashcards on Pipeline, created by Emma Tysk on 27/05/2017.
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- Emma Tysk
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