Fetch-Execute Cycle

Start

The program counter (PC) contains the address of the next instruction to be fetched

This address is copied from the PC to the Memory Address Register (MAR)

The instruction at this address is returned along the data bus to the Memory Buffer Register (MBR), PC increases by 1

Instruction gets copied into the Current Instruction Register (CIR). This is then decoded.

Instruction is split into opcode and operand, opcode determines type of instruction and hardware needed to execute it

If necessary, data may need to be fetched from memory and go to the MBR and then to the general purpose registers.

Instructions are executed by the ALU if necessary and results are stored in the general purpose registers

End