Chapter 7 Pipelining & RISC

Chapter 7 Pipelining & RISC

1. Instruction Execution Characteristics

   • 1. High-level languages (HLLs)
   • 2. Execution sequencing
   • 3. Semantic gap
   • 4. Operations performed
   • 5. Operands used

2. Implications

   • Three elements characterize RISC architectures
     • • Use a large number of registers
     • • Careful attention to the design of instruction pipelines
     • • Instructions should have predictable costs and be consistent with a high-performance implementation

3. CISC (Complex Instruction Set Computer)

   • 1. Two principal reasons for this trend
     • • simplify compilers
     • • improve performance
   • 2. Two advantages to smaller programs
     • • improve performance
     • • program takes up less memory

4. Characteristics of Reduced Instruction Set Architectures

   • 1. One machine instruction per machine cycle
   • 2. Register-to-register operations
   • 3. Simple addressing modes
   • 4. Simple instruction formats

5. RISC versus CISC Controversy

   • 1. Quantitative
     • • Compare program sizes and execution speeds of programs on RISC and CISC machines that use comparable technology
   • 2. Qualitative
     • • Examine issues of high level language support and use of VLSI real estate
   • 3. Problems with comparisons
     • • No definitive set of test programs exists
     • • Difficult to separate hardware effects from complier effects
     • • Most commercial devices advertised as RISC possess a mixture of RISC and CISC characteristics

6. Pipelining Strategy

7. Pipelining

   • Allow the execution of multiple instruction to overlap in time.

8. Non-pipelining

   • Next instruction is processed after the entire processing.

9. Additional Stages

   • Fetch instruction(FI)
   • Decode instruction(DI)
   • Calculate operands(CO)
   • Fetch operand(FO)
   • Execute instruction(EI)
   • Write operand(WO)

10. Pipelining of unequal stages

    • Always take the target of the stage delay to be the cycle time.
    • No stage overlap and latency must be constant
    • Instruction overlap is the same as the cycle time.

11. Pipeline hazards

    • Occur when pipeline, must all because conditions do not permit continued execution
    • Pipeline bubble

12. Three types of hazards

    • Resource
    • Data
    • Control

13. Data hazard

    • Read after write (RAW)
    • Write after read (WAR
    • Write after write (WAW)

14. Control hazard

    • branch hazard
    • Occurs when the pipeline makes the wrong decision on a branch prediction