Flashcards
Memory + Addressing Modes
Cards in this deck (25)
- 1What is the goal of memory and the 3 types?Efficiently store large amounts of data
DRAM
STRAM
ROM - 2How is memory structured?-Two dimensional array of bit cells, each ell stores one bit
N address bits and M data bits
2^N rows and M columns.
Depth: number of rows/words
Width: number of columns/word size
Array size: depth * width - 3What is a wordline?-Single row in memory array to be read or written
-Only one wordline is HIGH at once - 4What happens to the bitline on memory read?-If wordline is high, the stored bit drives the bitline value
-If wordline is low, the stored bit should not affect the bitline - 5What does memory consist of and what are the components of the interface between the CPU and memory?-Consists of latches, each holding a single bit value, at an address
-Memory Address Register (MAR) (holds the open address, the CPU activates the address line)
-MDR holds the activated data - 6When do READ and WRITE occur?-When wordline = 1 and Read/write line = 1
-When address line= 1 and read/write line =0 - 7Compare the characteristics of RAM and ROMRam:
-Volatile and memory lost in power off
-Dynamic RAM: dense but needs refreshing
-Static RAM: less dense but more stable
Rom:
-Memory persists during power off
-Modern ROM memory can be written to. - 8Draw a diagram at the transistor level of DRAM. How often do the capacitors need refreshing?
- 9Draw SRAM at the gate level.
- 10How does basic ROM work? Draw a diagram.
- 11How does programmable ROM work? darw its diagram
- 12What is multi-ported memory?Memory that can address more than one address line at once
- 13What are SRAM, DRAM, SSD and HDD used for, approx process speeds, and why?SRAM is used for cache. v expensive, 1ns access time
DRAM used for main memory. less expensive, 10ns access time
SSD is cheaper, 100,000ns access time
HDD cheapest, 10,000,000 access time
SSD and HDD used for virtual memory - 14What methods are used to improve memory access?-Wide path memory access (retrieve multiple bytes instead of one byte at a time)
-Memory interleaving: partition memory into subsections, each with its own address register and data register
-Cache memory - 15What is Wide Path Memory Access?-Call up multiple bytes (often 8) at a time
-Requires a wider memory-data bus and larger MDR
-8 bytes can be separated/used in the CPU using more circuitry
-Diminishing returns with more width due to less use and increased CPU complexity. - 16What is memory interleaving?-Dividing memory into separate chunks that can be accessed simultaneously
-Interleave, so consecutive addresses can be accecssed simultaneously
-Useful for pipelining - 17What is cache memory?-Preloading fastest memory with data most likey to use soon
-Typically data near addresses recently accessed
-Fastest memory is on the CPU itself, or SRAM. - 18What is direct addressing?Address read in the instruction is the address of the actual data
- 19What is immediate addressing?Address read in the instruction is the data to be used (suitable for constants eg 1)
- 20What is indirect addressingAddress read in the instruction points to the memory location containing the address of the actual data
- 21What is register indirect addressingThee address read in the instruction is the address of a register containing the address of the actual data
- 22What is indexed addressingThe address read in the instruction should have an index value (contained in some register) added to obtain the address of the data
- 23What is absolute addressing?The address read is the one the LM should go to (except for indexed addressing)
- 24What is relative addressingThe address read is an offset to the current instruction address (ie program counter value)
- 25What is Base offset addressingThe address read is offset by the current value in a special 'base' register
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- Flashcards on Memory + Addressing Modes, created by SEZ McKelvey on 11/04/2018.
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- SEZ McKelvey
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