Processor complexity study

Processor complexity study

1. Pipeline structures

   • Register rename logic
     • Related paper: Register File Design Considerations in Dynamically Scheduled Processors http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=501172
     • Map table
       • Map table is multiported and is function of the issue width. For example, 4 issue width processor with 2 read operands and 1 write operand will need to have 8 read ports and 4 write ports.
       • RAM implementation
         • 1) # of entries = # of architected logical registers 2) indexed with logical register number. Example: pr[lr] = 1
         • Questions???
           • Multiport SRAM: how it is implemented?
       • CAM implementation
     • Shadow table???
       • Refers to this paper, but the paper is about precise interrupts. Find on "shadow .." didn't give any results.
     • Dependence detection logic
   • Early processors implementation
     • PowerPC
       • http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=363071
       • Pipeline stages
         • Fetch
           • Fetch stage loads one of the fetch address to Fetch Address Register.
           • address can be generated at any pipeline stage
             • Fetch
             • Decode and Dispatch
               • At decode and dispatch, the stage can change the fetch address based on the Prediction logic.
             • Execute
               • At this stage branch is resolved, and in case of misprediction, the address changes to Branch Target Adress if "not taken" was predicted. And vise versa it changes to sequential address if "taken" was predicted.
             • Complete
               • At the complete stage: 1) the PC is updated to the taken target branch address or sequential address 2) or exception handler address
         • Decode
           • 4 instructions/cycle
           • Detect exception conditions
           • Check for resources
             • Execution unit
             • Source operands
             • Destination register
           • Branch
             • change fetch on unconditional
             • Predict based on BHT
       • Handling of precise interrupts
         • ROB
           • http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4607
           • ROB is one of the ways to implement precise interrupts
       • Questions
         • What are exceptions?
         • What is serialization in HW?
       • Renaming
         • Source operands
           • Source operands are not renamed. Only destination operands get renamed. 
           • When dealing with source operands, 3 things may happen: 1) source operands were not renamed, in which case, the actual values are read from register file. 2) source operands were renamed before so the renamed values are used. 3) source operands were renamed before, however the execution unit is till working on the result. The value is still dispatched with rename table identifier entry.
         • at what stage renaming happens?
       • Branch Prediction
         • Classic BHT
         • CTR???
           • The architecture of PowerPC provides special register to work with loops. In other words, if you use loops, make sure to work with this registers as it uses different mechanisms for prediction.
       • Common bus as in Tamotsulo
     • IBM System/360 Model 91
       • http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5392015
     • MIPS R10000
       • Paper: https://www.eecs.umich.edu/courses/eecs470/papers/R10000_Yeager.pdf
       • 1) Register renaming notes: * 
       • non-blocking caches. Allows cache access when miss is processed.
       • Pipeline stages
         • Renaming
           • Logical to physical register transformation.
           • Each physical register is written only once after assignment from the free list.
           • After the assignment and until data is written to register, the register is considered busy. Dependent instructions must wait until the register is ready. 
           • ONE INSTRUCTION CHANGES ONE PHYSICAL REGISTER ONLY ONCE. UNTIL IT GRADUATES (RETIRES). AFTER RETIRE THE PHYSICAL REGISTER IS FREE. PUT BACK IN THE FREE LIST.
           • Some research on Register renaming: https://www.jilp.org/vol2/v2paper10.pdf 
           • Hardware components
             • Map tables
               • 16 read port and 4 write port RAM implementation
               • FP map tables
               • Integer map tables
             • Free list
             • Active list
               • Keeps track of current active instructions
               • upto 32 active instructions is allowed
               • implementation: 4 parallel 8 deep circular FIFOs
               • Questions???
                 • The instruction is identified by a tag. Tag is an address of the instruction in the active list. Now, how does the FIFO implementation helps? What happens when the instruction is sandwiched between 2 other uncompleted instructions?
             • Busy bit tables

2. Load hit speculation

   • based on CMPE202 class and lectures. https://classes.soe.ucsc.edu/cmpe202/Spring16/SECURE/11ooo.mp4 @minute 45-46
   • 10-30% slow down if not implemented
   • Queues
     • Load Q
     • Store Q(address)
     • Store data Q
     • OoO stores and loads
       • It is OK to perform loads and stores out of order if there is no RAW dependence.