CHAPTER 7: PIPELINING & RISC

CHAPTER 7: PIPELINING & RISC

1. Pipelining Strategy

   • -It improve CPU overall system performance
   • -To apply this concept to instruction execution we must recognize that an instruction has a number of stages

2. Pipelining

   • -It is a key implementation technique used to build fast processors that seen in RISC
   • -It allows the execution of multiple instructions to overlap on time

3. 6 Type of Additional Stages

   • Fetch instruction(FI)
     • Read the next expected instruction into a buffer
   • Decode instruction(DI)
     • Determine the opcode and the operand specifiers
   • Calculate operands(CO)
     • Calculate the effective address of each source operand
   • Fetch operands(FO)
     • Fetch each operand from memory
   • Execute instruction(EI)
     • Perform the indicated operation and store the result
   • Write operand(WO)
     • Store the result in memory

4. Timing Diagram

   • n = number of instuction
   • k = stages
   • T = seconds

5. Pipelining of Unequal stages

   • -Always take the largest of the stage delay to be the cycle time
   • -No stage overlaps and the latency must be constant
   • -Ensure that instruction overlap is the same as the cycle time

6. Pipeline hazards

   • Also known as pipeline bubble
   • Data hazard -occurs when there is conflict in the access of an operand location
     • Types of data hazard-RAW,WAR,WAW
   • Resource hazard-occurs when two or more instructions that are already in pipeline read the same source
   • Control hazard(branch hazard)-occurs when the pipeline makes the wrong decision on a branch prediction

7. Instruction Execution Characteristics

   • EXECUTION SEQUENCING
   • HIGH-LEVEL LANGUAGES(HLLs)
   • SEMANTIC GAP
   • OPERANDS USED
   • OPERATIONS PERFORMED

8. Characteristics of RISC

   • One machine instruction per machine cycle
   • Register-to-register operations
   • Simple addressing modes
   • Simple instruction formats