Component 2.1 - Hardware and Communications

Component 2.1 - Hardware and Communications

1. INPUT/OUTPUT

2. Von Neumann architecture

   • FDE Cycle
   • Inside the CPU
     • Control Unit
       • Manages the FDE Cycle
     • Arithmetic logic Unit
       • Processes and manipulates data which consists of arithmetic or logical comparisons. allows decisions to be made.
     • Registers
       • temporary data stores within the CPU, used primarily in the FDE cycle.
         • notable registers are the Memory Address Register, Memory data register, Program Counter, Accumulator and Current instruction Register.
           • MDR
             • holds the code read from the currently addressed memory location
           • CIR
             • holds the most recently fetched program instruction.
           • PC
             • Points to the location of the next instruction for the CU to execute.
           • MAR
             • The Memory Address Register is used during the FDE cycle to hold the address of the currently accessed memory location.
           • ACC
             • Holds data that is part of calculations.

3. Protocol

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