The CPU, Instruction Fetch & Execute

The CPU, Instruction Fetch & Execute

1. A Bog Standard Architecture

   • The CPU contains
     • a number of registers
     • an arithmetic logic unit
     • the control section
     • connections to the memory by two buses,
     • internal buses or data pathways
   • CPU Registers
     • Memory Address Register
       • The MAR is used to store the address to access memory.
     • Memory Buffer Register
       • The MBR stores information that is being sent to, or received from, the memory along the bidirectional data bus.
     • Accumulator
       • The AC is used to store data that is being worked on by the ALU, and is the key register in the data section of the cpu.
     • Program Counter
       • Connected to the internal address bus, the PC holds the address in memory of the next program instruction.
     • Instruction Register
       • When memory is read, the data first goes to the MBR. If the data is an instruction it gets moved to the IR. The IR has two parts:
         • IR (opcode)
           • This the genuine instruction part of the instruction, that tells the cpu what to do
         • IR (address)
           • The least significant bits of the instruction are actually data. They get moved to IR (address). As the name suggests they usually form all or part of an address for later use in the MAR.
     • Stack Pointer
       • The SP is connected to the internal address bus and is used to hold the address of a special chunk of main memory used for temporary storage during program execution.
     • All Registers
       • The registers comprise nothing more than a row of Dtype latches which share a common clock input providing temporary storage on the CPU. Because these registers output onto buses they have tri-state buffers are connected to a single input OE, for “Output Enable”
   • Units in the CPU
     • Control Unit
       • The CC is responsible for the timing and execution of the various register transfers required to fulfill an instruction held in the IR.
     • Arithmetic Logic Unit
       • The ALU is responsible for bit operations on data held in the AC and MBR and for storing the results. It contains arithmetic adders, logical AND-ers and OR-ers, and so on.
     • Status Register
       • Closely associated with the ALU is the SR or Condition Control Word or Status Word. It is not quite the same as the other registers in that it really just a collection of 1bit flags that indicate the outcome of operations that the ALU has just carried out.
   • Buses, registers, and their widths
     • The buses carry words of information which are many bits wide, and on diagrams a bus is indicated either by a wide line, or by a single line with a dash through it often accompanied by the bus width in bits.
       • Data
         • Microcontrollers have data bus widths of 4 bits, 8-bits, 16-bits and 32-bits, while the most advanced PCs use 64 bits. We will assume that the “memory width” is 16 bits or 2 Bytes. This means that each location can store 2 Bytes. We will also assume that the data bus is 16 bits wide, and the MBR and AC registers on the data side of the CPU are therefore also 16 bits wide. The ALU is also 16 bits wide.
       • Address
         • The address bus does not have to be the same width as the data bus. The width on CPUs over time has increased in step with contemporary memory technology, Having n address lines means that that there are 2n addresses or locations in the address space
           • The IR is special. The IR (opcode) part should be wide enough to take the largest opcode. We assume the opcode is a fixed 8 bits wide, allowing 256 different instructions — which is plenty enough. The IR (address) part has to have the same width as the address bus, 24 bits.
   • Introduction to the Main memory
     • The memory will comprise mostly random access memory (RAM) with some additional read-only memory (ROM) to help the machine start up. The main memory does not reside in the cpu chip but sits on the motherboard and is connected to the cpu via a bus — in fact two (or three) buses, the data bus and address bus (and also a control bus).
       • The main memory is effectively just a large stack of registers, each with its own address.

2. The Fetch, Decode, Execute Cycle

   • We want our CPU repeatedly to
     • FETCH the next instruction from memory into the instruction register
     • DECODE the instruction
     • EXECUTE the instruction
   • Fetching and an Executing an instruction simply require the CPU’s Control Section to issue Levels and Pulses which set up pathways and fire register transfers so that
     • Data is moved from memory to registers, and between registers
     • Data is passed (sometimes) through the ALU
     • Data is stuffed back into the memory