Architecture Vs Organisation

Architecture Vs Organisation

1. Architecture

   • Attributes visible to programmer
     • Instruction set
     • Num of bits used for data representation.
     • I/O mechanism
     • Addressing techniques

2. Organization

   • How features are implemented
     • Control signals
     • Interfaces
     • memory Technology

3. Comp Arch & Cloud comp

   • Hardware Vs Software
     • Memory
       • The CPU exchanges data with memory. For this purpose, it typically makes use of two internal (to the CPU) registers: a memory address register (MAR), which specifies the address in memory for the next read or write, and a memory buffer register (MBR), which contains the data to be written into memory or receives the data read from memory. Similarly, an I/O address register (I/OAR) specifies a particular I/O device. An I/O buffer (I/OBR) register is used for the exchange of data between an I/O module and the CPU.
       • A memory module consists of a set of locations, defined by sequentially numbered addresses. Each location contains a binary number that can be interpreted as either an instruction or data. An I/O module transfers data from external devices to CPU and memory, and vice versa. It contains internal buffers for temporarily holding these data until they can be sent on.
     • InstructionCycle
       • Cycle of computer. Retrieves program from CPU and decides what action is required. Continuous loop.
       • Two steps; Fetch, execute
         • • Fetch Cycle: Program Counter (PC) holds address of next instruction to fetch. Processor fetches instruction from memory location pointed to by PC Increment PC Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions
           • Execute cycle: Processor-memory data transfer between CPU and main memory Processor I/O Data transfer between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations Mix of each of above….
             • Program Execution
       • State Diagram
         • State Diagram
     • Interrupts
       • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program e.g. overflow, division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O from I/O controller Hardware failure e.g. memory parity error
         • Program
         • Timer
         • I/O
         • Hardware failure
       • Interrupt Cycle: Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program
       • Multiple Interrupts: Disable interrupts Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur Define priorities Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

4. Processors

   • Intel x86 family share same basic arch
   • IBM System/370 family share same basic arch
   • Gives code compatibility
   • Orginization differs between diff versions

5. Structure & Function

   • Structure: Components relate to each other
     • Logical Structure:
       • BIOS: Basic input/output system
         • Software
           • Identifies system devices (Hardware)
           • Locates boot loader, loads & executes. Giving it control of PC.
           • Stored on flash memory on chip on motherboard
       • CPU
         • CPU
           • Located on motherboard
             • Carries out commands.
             • Speed is number of instructions per second.
       • Memory / RAM
         • Short term memory
           • Volatile: No power no memory
       • Hard disk
         • Long term storage
       • Input / output Device
       • Comm channel eg USB
       • BUS (High Speed Internal Comm)
     • Motherboard: Comps main circuit board
     • Power supply
     • Top Level
       • CPU: Controls operation of computer
       • Main memory: Stores data.
       • I/O: Moves data from comp to external environment
       • Sys interconnections: Mech that provide comm between CPU, main memory and I/O. eg BUS
       • • Control unit: Controls operations
         • Arithmetic & logic unit: Data processing func
         • Registers: Internal storage to CPU
         • CPU Interconnection: Communication between CU ALU &register
   • Function: Operation of individual components as part of the structure
   • Function: operation of individual components as part of the structure
     • Data Processing
       • Data is either: Stored, Processed
     • Data Storage
       • Read or Write
     • Data movement
       • Func as data movement device.

6. System bus: Different task depending on correct control signal.

7. Programs: sequence of steps. each step arithmetic or logical operation done.

8. Func of CU: Each operation unique code provided. Hardware seg accepts code & issues control signals

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