Notes
CPU Architecture - created from Mind Map
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Purpose of CPU
CPU Components
Registers
CPU Performance
Vonn Neumann Architecture
Fetch
Decode
Execute
Cache
Control unit
Arithmetic logic unit
High-speed memory
Controls information flow
Calculation and logic
Memory Address Register
Memory Data Register
Program Counter
Accumulator
Definition
Stores current address
Recently fetched data
Stores next address
Stores ALU results
High speed memory
Clock speed
Cache
Cores
Regular synchronisations
High speed memory
Processes FDE Cycles
Data instructions together
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- Note on CPU Architecture - created from Mind Map, created by Callum Hart on 20/09/2022.
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- Callum Hart
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- Created by Callum Hart · Sep 20, 2022
- Copied to Note by Callum Hart · Sep 20, 2022
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