Direct Memory Access (DMA)

Page 1

The CPU can request data from an I/O controller one byte at a time, but doing so wastes the CPU's time.

We assume that the CPU accesses all devices and memory via a single system bus that connects the CPU, the memory, and the I/O devices.

The DMA controller has access to the system bus independent of the CPU.

It contains several registers that can be written and read by the CPU. These include memory address register, a byte count register, and one or more control registers.

Control register specify the I/O port to use, the direction of the transform (read or write), the transfer unit (byte or word) and the number of bytes to transfer in one burst.

Many buses can operate in two modes;

word-at-a-time

block

Cycle stealing : In the former mode, the operation is: the DMA controller requests the transfer of one word and gets it. If the CPU also wants the bus, it has to wait.

Burst mode : In block mode, the DMA controller tells the device to acquire the bus, issue a series of transfers, then release the bus.