Mapa mental
COE 321: Logic Design
Contenido del mapa
COE 321: Logic Design
Combinational Part
- Boolean Algebra
- Logic Gates
- K-maps
- Simplification
- Quine-McCluskey
- S-O-P & P-O-S
- Canonical Forms
- Gate Delay
- Verilog
- Technologies
- Multiplexers
- Decoders
- PLA's
- PAL's
- ROMs
- Designs
- Adder Design
Sequential Part
Assesment: Discrete Structures
MOS Transistors
- n-mos
- p-mos
Gates
- AND
- OR
- NOT
- NOR
- NAND
- XOR
- XNOR
Información
- Descripción
- Mapa Mental sobre COE 321: Logic Design, creado por elio.saliba el 26/12/2014.
- Creado por
- elio.saliba
- Visitas
- 2
- Valoración