Mind map
COE 321: Logic Design
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COE 321: Logic Design
Combinational Part
- Boolean Algebra
- Logic Gates
- K-maps
- Simplification
- Quine-McCluskey
- S-O-P & P-O-S
- Canonical Forms
- Gate Delay
- Verilog
- Technologies
- Multiplexers
- Decoders
- PLA's
- PAL's
- ROMs
- Designs
- Adder Design
Sequential Part
Assesment: Discrete Structures
MOS Transistors
- n-mos
- p-mos
Gates
- AND
- OR
- NOT
- NOR
- NAND
- XOR
- XNOR
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- Mind Map on COE 321: Logic Design, created by elio.saliba on 26/12/2014.
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- elio.saliba
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