Test
EndArchi
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Preguntas del test (20)
1Which of the following can be described using Verilog?
- AHardware concurrency
- BParallel Activity Flow
- CSemantics for Signal Value and Time
- DAll of the above
2Which of the following could be fulfilled using Verilog models?
- Adocumentation
- Btesting using simulation
- Cformal verification
- DAll of the above
3Gate scheme of your circuit is usually defined on following level
- AStructural
- BFunctional
- CGeometric
- DNone of the above
4What is g1 in following verilog statement? and #5 g1 (f1, a, nsel);
- AFunction name
- BInstance name
- CDelay
- DNone of the above
5Which verilog module contains sample data to evaluate logic of design module?
- AStructural
- BTest
- CTest bench
- DNone of the above
6What data type in Verilog corresponds to implicit storing of elements?
- ARegister
- BNet
- CModel
- DNone of the above
7What is default value of register in Verilog?
- A0
- B1
- Cx
- DNone of the above
8To access all 4bits of net test declared as wire [3:0] test; following will be used
- Atest[4:1]
- Btest[4]
- Ctest
- DNone of the above
9If we make parallels with Object-Oriented Programming then instantiating Verilog module without specifying it’s params will be same as usage of
- Adestructor
- BDefault constructor
- CParameterized constructor
- DNone of the above
10When does blocking assignment (=) takes place?
- AAt the end of the block
- BAt the end of module
- CImmediately
- DNone of the above
11Which of the following statements about Verilog is false?
- AIt’s low level language for digital system design
- BProgramming style resembles C language
- CIt’s supported by numerous CPU vendors including Intel
- DCan be used for both modelling and simulating digital systems
12How many levels Verilog modelling have?
- A1
- B2
- C3
- D4
13Code describing logics and algorithm of your circuit is usually defined on following level
- AStructural
- BFunctional
- CGeometric
- DNone of the above
14What Verilog models describes logic of circuit using gate primitives?
- ATest
- BSctuctural
- CTest bench
- DNone of the above
15Which verilog module is used to connect module describing logic of circuit and module containing sample data to evaluate that logic?
- ADesign
- BTest
- CTest bench
- DNone of the above
16What data type in Verilog corresponds to making physical connection between different components of circuit?
- ARegister
- BNet
- CModel
- DNone of the above
17If you use undeclared variable in Verilog, then by default it’s type will be
- Aregister
- Bwire
- Cparameter
- DNone of the above
18To access 4th bit of net test declared as wire [3:0] test; following will be used
- Atest[3:0]
- Btest[3]
- Ctest[0:3]
- DNone of the above
19What is #(4,5) in following Verilog declaration modXnor #(4, 5) G2 (y2_out, b2, c2) ?
- AInstance name
- BModule name
- CDelay
- DNone of the above
20When does non-blocking assignment (<=) takes place?
- AAt the end of the block
- BAt the end of module
- CImmediately
- DNone of the above
Información
- Descripción
- Engineering Test sobre EndArchi, creado por Алишер Хасен el 15/12/2018.
- Autor
- Алишер Хасен
- Idioma
- English
- Visitas
- 6
- Historial
- Creado el 15 dic 2018 · actualizado el 15 dic 2018
- Etiquetas
- Valoración
- Aún sin valoraciones Valora este test