GoConqr has a new look! Let us know what you think.

Sign up free

Flashcards

Architecture and Networks

Jojo O'Gorman Computer Science English 132 cards

Cards in this deck (132)

  1. 15 WAYS HOSTILE ACTORS CAN COMPROMISE A NETWORK1) MAINTENANCE THREATS - sabotaging the equipment and cables
    2) ELECTRICAL THREATS - interfering with the power supplies e.g. voltage spikes
    3) ENVIRONMENTAL THREATS - Creating temperature anomalies, dust, radiation
    4) REMOTE/LOCAL ACCESS THREATS - unauthorised login
    5) PHYSICAL THREATS - physical damage to devices and theft
  2. 2DATA ENCRYPTIONAn encryption algorithm is applied to the known data, the plaintext, to generate the ciphertext.
    A decryption algorithm is then needed to decrypt the ciphertext back into plaintext.
  3. 3SYMMETRIC KEYThe same key is used for both encryption and decryption. This is made public between both the sender and the receiver. If the key is stolen, the scheme is easily defeated.
  4. 4ASYMMETRIC KEYUses one key for encryption, which is made public to the sender, and a different key for decryption, kept private by the receiver. The sender cannot decrypt the data once encrypted. Each user has to generate a pair of keys and then publish their public key so that people can send encrypted messages to them.
  5. 5PEN-TESTINGAuthorised, simulated attacks on a computer system, looking for security weaknesses, potentially gaining access to the system's features and data.
  6. 6WHITE BOX PEN-TESTINGTests internal structures/systems
  7. 7BLACK BOX PEN-TESTINGTests functionality
  8. 8DENIAL OF SERVICE (DOS) ATTACKSFloods a service/application with unwanted packets so that the affected systems are put out of business due to the workload being processed.
  9. 9SYN ATTACKMost common form of DOS attack, based on the packet used when a TCP connection is established.
    Some firewalls can now detect these types of attacks taking place.
  10. 10DNS FAST FLUX ATTACKUsed by botnets to hide phishing/malware delivery sites behind an ever-changing network of compromised hosts acting as proxies.
    Numerous IP addresses associated with a single fully qualified domain name, where IP addresses are swapped at high frequency through changing DNS records.
  11. 11von NEUMANN MODELData is transferred between:
    PROCESSING UNIT
    CONTROL UNIT
    MEMORY (data + instructions)
    INPUT/OUTPUT DEVICES
    via a BUS
    (cannot be used in parallel to avoid bottleneck)
  12. 12CENTRAL PROCESSING UNIT (CPU) Tasks:- Loads instructions and decodes them
    - Loads data into registers
    - Computes arithmetic and logical operations on registers according to the current instruction
    -Stores data from registers
  13. 13MICROPROCESSOR CHIPA digital integrated circuit (IC) and CPU.
    Has no RAM, ROM or IO ports.
    Needs to be placed on a motherboard to where RAM is based.
    Needs data buses on the motherboard to access RAM and other peripherals.
  14. 14MICROPROCESSOR CHIP Tasks:- Load instructions and data into registers
    - Compute arithmetic and logical operations on registers.
    - Store data back from registers
  15. 15MICROCONTROLLERA small computer system in an integrated circuit chip - System on Chip (SoC).
    Has a CPU, RAM, ROM, I/O Ports and timers on chip.
    Size of memory is fixed and is not expandable.
  16. 16INSTRUCTION SET ARCHITECTURE (ISA)ISA describes the set and format of instructions supported by a CPU.
    Is only an interface, has to be implemented in the Microarchitecture.
  17. 17ASSEMBLY LANGUAGEA procedural language used to represent machine instructions and data. There is a one-to-one correspondence between a line of assembler and a machine instruction.
  18. 18FORMAT OF ASSEMBLY INSTRUCTIONSinstruction arg1, arg2
    arg1, arg2 could be registers, memory addresses or constants
  19. 19REGISTER INSTRUCTION POINTER (RIP)This register contains a 64-bit memory address of the currently executed instruction (similar to the pointed to the current state in a Turing Machine).
  20. 20GENERAL PURPOSE REGISTERSRAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, R8, R9, R10, R11, R12, R13, R14, R15
    are all 64-bit general purpose registers.
  21. 21ARITHMETIC INSTRUCTIONSADD, INC, MUL, DIV, SHIFT
    e.g.
    ADD RAX, 2
    adds 2 to RAX register
  22. 22DATA TRANSFER INSTRUCTIONLOAD/STORE data from memory/a register
    e.g.
    MOV RAX, [RBX]
    Move the 8 bytes in memory at the address contained in RBX to RAX
  23. 23CONTROL TRANSFERBRANCHES
    Used to choose the next instruction to be executed
  24. 24FLAG REGISTERSContain the results of a comparison operation. Usually used by a control transfer instruction
    e.g.
    CMP RDX, 00
    JE L7
    Compares the DX value with zero, if yes, then jump to label 7
  25. 25VECTOR INSTRUCTIONSUsed to execute instructions in parallel
    e.g.
    ADDSS xmm0, xmm1
  26. 26VECTOR REGISTERSSpecifically used for vector operations
    e.g.
    ADDSS xmm0, xmm1
  27. 27MIPSMicroprocessor without Interlocked Pipeline Stages
  28. 28MIPS PROPERTIESInstructions are composed of an operation acting on operands.
    MIPS has 32 general purpose registers and 32 floating point registers.
    MIPS ISA is a load-store architecture, meaning that the ONLY operations that interact with memory are LOAD and STORE.
  29. 29RISCMIPS is a Reduced Instruction Set Architecture because it has a relatively small set of instructions.
  30. 30RISC vs CISCPrimary goal of CISC is to complete task in as few lines as possible. Therefore CPU hardware is more complex.
    RISC processors only use simple instructions executed within one clock cycle. Therefore more lines of assembly are needed to complete a task.
  31. 31MIPS MEMORYMemory is composed of byte addressable 1 dimensional array. Each location is one byte (8 bits). A memory address indexes into the array.
  32. 32MIPS OPERATIONSDATA TRANSFER - load/store
    ARITHMETIC AND LOGICAL - add, sub, div, mul, cmp
    FLOATING POINT ARITHMETIC - add, sub, div, mul
    CONTROL - if, branch
  33. 33LOAD A VALUE FROM MEMORYCopy the data from memory into a register
    e.g.
    LW $4, 12($29)
    Loads one word from memory location $29 + 12 offset, to register 4
  34. 34STORE A VALUE TO MEMORYCopy the data from a register to memory
    e.g.
    SW 12($29), $4
    Stores one word to memory location $29 + 12 offset, from register 4
  35. 35LOAD INSTRUCTIONLB = LOAD BYTE (8 bits)
    LH = LOAD HALF-WORD (2 bytes)
    LW = LOAD WORD (4 bytes)
    LD = LOAD DOUBLE WORD (8 bytes)
  36. 36MIPS: 5 STAGE EXECUTION MODEL1) FETCH
    2) DECODE
    3) EXECUTION
    4) MEMORY
    5) WRITE BACK
  37. 371) FETCHSend out the current address to the program counter.
    Fetch the instruction from memory into the instruction register.
  38. 382) DECODEDecode the instruction and access the register file to read present registers.
  39. 393) EXECUTIONThe ALU operates on operands prepared in step 2.
  40. 404) MEMORYAccess memory if needed, perform load or store.
  41. 415) WRITE BACKWrite the result back to the register file.
  42. 42PERFORMANCE=
    (INSTRUCTIONS/PROGRAM)
    *
    (CYCLES/INSTRUCTION)
    *
    (TIME/CYCLE)
  43. 43ATOMIC AND SEQUENTIAL EXECUTIONATOMIC = an instruction is executed completely in one unit
    SEQUENTIAL = list of instructions executed one after another
  44. 44PIPELININGIt would be too slow for processors to execute instructions atomically and sequentially.
    Technique of pipelining is used to speed up internally.
    Multiple instructions are overlapped in execution, taking advantage of parallelism that exists among the steps.
  45. 45ILPProcessors use pipelining to overlap instructions to improve performance. This overlap of instructions is
    INSTRUCTION LEVEL PARALLELISM
    (ILP)
  46. 46PIPELINING EXAMPLESWhen an instruction is being DECODED, FETCH the next instruction.
    When an instruction is being EXECUTED, DECODE the next instruction.
    When an instruction is accessing MEMORY, EXECUTE the next instruction.
    When an instruction is WRITING BACK its result, access MEMORY for the next instruction.
  47. 47PIPELINING: OVERALL CONCEPTWhen an instruction is using some resources in its processing phase, process other instructions on idle resources not needed by that instruction.
  48. 48PIPELINING STEPS1) Divide the instruction processing cycle into distinct 'stages' of processing.
    2) Ensure enough hardware resources to process one instruction at each stage.
    3) Process a different instruction in each stage.
  49. 49PIPELINING: LIMITATIONSThere is a max length to depth of pipeline, ultimately defined by hardware resources available.
    When we hit a dependancy during execution, we STALL the pipeline. The CPU needs to dump and reload its state, which lead to LATENCY in execution.
  50. 50HAZARDSThe situation where there are problems with the instruction pipeline in CPU microarchitecture.
    i.e. when the next instruction cannot execute in the following clock cycle.
  51. 51DATA HAZARDSInstructions that exhibit data dependance to modify data in different stages of a pipeline.
  52. 52STRUCTURAL HAZARDSTwo stages in the pipeline need to access some hardware component which causes a queue. There is a limit to how much hardware can be implemented on the chip.
  53. 53CONTROL FLOW HAZARDSThe processor doesn't know the outcome of the branch when it needs to insert a new instruction into the pipeline (typically at the fetch stage).
  54. 54WHY A MEMORY HIERARCHY?Need unlimited amounts of memory with low latency. Fast memory is more expensive per bit than slower memory, therefore the solution is to organise memory into a hierarchy.
  55. 55HIERARCHY CONCEPT-----------> Entire addressable memory space available in largest, slowest memory.
    ---> Incrementally smaller & faster mems, each containing a subset of the memory below it, proceed in steps up toward the processor.
    Gives the illusion of a large, fast memory being presented to the processor.
  56. 56RELATIVE COSTSCPU (most expensive)
    |
    LEVEL 1 CACHE
    |
    LEVEL 2 CACHE
    |
    MAIN MEMORY (cheapest)
  57. 57CACHE - MISSESIf a load instruction cannot find a word in CACHE, a MISS occurs. The next steps are:
    - FETCH the word from a lower level hierarchy, adds a time delay (HIGHER LATENCY REFERENCE)
    - FETCH words close to that ref word- SPATIAL LOCALITY - in the likelihood that the next operation will access them.
    - Keep the fetched words in a CACHE.
  58. 58DYNAMIC RAM (DRAM)Data is stored by charging or discharging the cell capacitor to its desired voltage.
    VOLATILE MEMORY - loses its data quickly when power is removed.
  59. 59DRAM REFRESH CYCLEThe electric charge on the capacitors slowly leaks off, so to prevent the loss of data, DRAM has an external memory refresh circuit which periodically rewrites the data in its capacitors.
  60. 60STATIC RAM (SRAM)SRAM uses bistable latching (flip flops) to store bits. Each cell stores bits on transistors.
    Two additional access transistors serve to control the access to a storage cell during read/write operations.
    Also, VOLATILE, however BBSRAM (battery-backed SRAM) can retain data when power supply is off.
  61. 61SRAM vs DRAMSRAM requires low power to retain bits and 6 transistors per bit. Does not require a refresh cycle.
    SRAM is used for CACHE
    DRAM must be rewritten after being read and periodically refreshed every ~8ms and requires 1 transistor per bit.
    DRAM is used for MAIN MEMORY
  62. 62CALCULATING DIMM NAME FOR DDR3 SDRAMx = clock rate * 2 * no of bytes
    Naming convention = PCx
  63. 63DDR OPTIMIZATIONSDDR2
    2.5 - 1.8 V, (266MHz, 333 MHz, 400MHz)
    DDR3
    1.34V, 800MHz
    DDR4
    1-1.2V, 1600MHz
  64. 64FLASH MEMORYA type of EEPROM, read only memory whose contents can be erased and reprogrammed using a pulsed voltage.
    Must be erased before being overwritten.
    NON-VOLATILE so retains data after power is removed.
  65. 65DEPENDABILITY - soft/hard errorsMemory is susceptible to cosmic rays - particles can interact and flip bits or erase them completely.
    SOFT ERROR - dynamic errors detected and fixed by error correcting codes (ECC)
    HARD ERROR - permanent errors, use sparse rows to replace defective rows.
  66. 66VIRTUAL MEMORY- Each program operates as if it has full access to memory.
    - OS performs mapping functions that relate program addresses in virtual memory to actual physical memory address.
  67. 67VIRTUAL MEMORY: Pros/ConsPROS - Programs largely freed from memory hierarchy
    CONS - Need hardware support to manage the mapping known as the Memory Management Unit. Very complex OS code needed to handle mapping.
  68. 68MEMORY MANAGEMENT UNITS (MMUs)- Divide the virtual address space into pages. The bottom bits of the addresses are left unchanged, and the upper address bits are the virtual page number.
    - The MMU is programmed by the boot loader at startup
  69. 69PAGE TABLE ENTRY (PTE)- MMUs use an in-memory table of pages containing one page table entry (PTE) per page, to map virtual page numbers to physical page numbers in memory.
  70. 70TRANSLATION LOOKASIDE BUFFER (TLB)- An associative cache of page table entries (PTEs).
    - Used to avoid the necessity of accessing the main memory every time a virtual address is mapped.
  71. 71VIRTUAL MACHINES- Allows different ISAs and operating systems to be presented to use programs.
    - System Virtual Machine software is called 'virtual machine monitor' and individual VMs running under the monitor are called 'guest VMs'.
  72. 72IMPACT OF VIRTUAL MACHINES ON VIRTUAL MEMORY- Each guest OS maintains its own set of page tables
    - Virtual Machine Monitor adds a level of memory between physical and virtual called 'Real'
    - VMM maintains shadow page table that maps guest virtual addresses to physical addresses.
  73. 73IEEEINSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS
    - Issue MAC addresses
    - IEEE offers Registration Authority programs or registries which maintain lists and unique identifiers under standards and issue UIs to those wishing to register them.
  74. 74DHCPDYNAMIC HOST CONFIGURATION PROTOCOL
    The IP address of a device is managed in software. When a device connects to ethernet/Wifi it is either:
    1) Configured with a predefined static address
    2) Requests an IP address from DHCP server on the network
  75. 75DHCP dialogueClient sends DISCOVER ----------------->
    <------------------- Server sends OFFER
    Client sends REQUEST ----------------->
    <--------- Server sends ACKNOWLEDGE
  76. 76DHCP dialogueComputer sends a UDP packet onto the network. Since IP of DHCP server is also unknown:
    SOURCE IP = 0.0.0.0
    DEST IP = 255.255.255.255
  77. 77IANAINTERNET ASSIGNED NUMBERS AUTHORITY
    - Issue IP addresses
    - Responsible for global co-ordination of the Internet Protocol addressing systems.
  78. 78IPv4 ADDRESSESEach NIC on the internet has a globally unique 32-bit address. This is split into:
    1) NETWORK ADDRESS
    2) HOST PART
  79. 79IP CLASSESCLASS A CLASS B
    0 - 126 128 - 191
    CLASS C CLASS D
    192 - 223 224 - 239
    CLASS E
    240 - 255
  80. 80OSI 7 LAYER MODELAPPLICATION
    PRESENTATION
    SESSION
    TRANSPORT - TCP/UDP
    NETWORK - IP/ARP/RARP
    DATA LINK
    PHYSICAL
  81. 81SUBNET MASKING- Write IP in binary
    - Write netmask in binary
    - Perform AND operation to give network address
    - Remaining part forms host part
    - Calcluate max hosts in dec
  82. 82IP HEADER: VERSIONContains the version of the Internet Protocol the header relates to
    i.e. IPv4
  83. 83IP HEADER: IHLINTERNET HEADER LENGTH:
    - Number of 32-bit words in header. Minimum of 5 (5 x 32 = 20 bytes)
  84. 84IP HEADER: DSCPType of service
  85. 85IP HEADER: TOTAL LENGTHTotal length of the packet measured in octets and includes both header and data.
  86. 86IP HEADER: IDENTIFICATIONValue assigned to aid in assembling fragments.
  87. 87IP HEADER: FLAGSVarious control flags
    e.g. 0 = may fragment
    1 = do not fragment
  88. 88IP HEADER: FRAGMENT OFFSETIndicates the position of the fragment within the packet.
  89. 89IP HEADER: TIME TO LIVEMaximum time the datagram is allowed to remain in the internet system.
    If this field is zero, then the datagram must be destroyed.
    Causes undeliverable datagrams to be discarded.
  90. 90IP HEADER: PROTOCOLIndicates the next level protocol used in the data portion of the IP datagram
    e.g. TCP/UDP
  91. 91IP HEADER: HEADER CHECKSUMSimple checksum. Protects the header against data corruption.
    Should be zero for no corruption.
  92. 92IP HEADER: SOURCESource IP address - 32 bits
  93. 93IP HEADER: DESTINATIONDestination IP address - 32 bits
  94. 94IP HEADER: OPTIONSExtra optional fields - up to 60 bytes
  95. 95UNICASTINGA computer talks to one other computer
    e.g. web browser ----> server
    Enabled with TCP or UDP at layer 4
  96. 96MULTICASTINGA computer sends the same message to several computers
    e.g. stock exchange ------> brokers
    Enabled with UDP multicast at layer 4
  97. 97MAC ADDRESSMEDIA ACCESS CONTROL ADDRESS
    - Hardware address given to every NIC when manufactured.
    - Used at layer 2 to communicate on the local network
    6 bytes long:
    3 bytes - organisationally unique identifier
    3 bytes - set by manufacturer
  98. 98ADDRESS RESOLUTION PROTOCOL (ARP)To send a data packet to a known IP, MAC address must be found so that layer 2 packet can be built. The ARP asks the LAN:
    Who has following IP address, Tell me your MAC address.
  99. 99ARP CACHETo reduce network traffic, ARP software saves info from responses to use for subsequent packets. Saved in memory as cache, ARP searches cache before using network.
  100. 100REVERSE ADDRESS RESOLUTION PROTOCOL (RARP)If hardware (MAC) address is known, RARP does reverse of RARP and retrieves IP address. Uses IP address that is broadcasted when diskless workstation boots up.
    RARP compare network address to configuration file to obtain IP and sends this back to client.
  101. 101NETWORK/PORT ADDRESS TRANSLATION (NAT/PAT)Certain addresses in the IPv4 protocol are reserved for private use and should NEVER be routed onto the public internet.
    We may build a private network and then connect it to the public internet using NAT/PAT
    Private addresses are translated to IPs that CAN be routed onto the public internet
  102. 102RFCREQUEST FOR COMMENTS
    - Produced and published by the IETF
  103. 103RFC FOR INTERNET PROTOCOL?RFC791
  104. 104RFC FOR TRANSMISSION CONTROL PROTOCOL?RFC793
  105. 105RFC FOR USER DATAGRAM PROTOCOLRFC768
  106. 106ROUTINGRouters exchange info with each other using routing protocols
    e.g. OSPF and RIP
    In addition to IP addresses, they send info such as:
    Administrative distance
    Metric
  107. 107ADMINISTRATIVE DISTANCEA level of trustworthiness of the information
  108. 108METRICA crude estimate of distance or latency
  109. 109LINK-STATERouters use OSPF to tell each other all the links on their network, presented as a GRAPH. Each router computes the shortest path and updates its own routing table.
    The link-state messages are broadcast at set intervals and when a link goes up/down.
  110. 110OSPFOPEN SHORTEST PATH FIRST - aim is to have the whole network converge quickly.
    OSPF is good at ensuring convergence.
  111. 111ROUTING TABLEThe key to evaluating the interface on which the packet should be forwarded is to find the
    LONGEST MATCH IN THE ROUTING TABLE FOR THE DESTINATION ADDRESS.
  112. 112ROUTING TABLE TIE-BREAKERIf there are two or more equivalent matches then apply tie-breaker:
    If AD is different - Choose entry with lowest
    Else, if AD the same - Choose entry with lowest METRIC
  113. 113TCPTRANSMISSION CONTROL PROTOCOL - Layer 4
    - Maintains reliable connections between hosts
    - Manages efficient packaging and transmission of network traffic
  114. 114TCP PROPERTIESVIRTUAL CIRCUITS - TCP connections are like live, two-way connections between hosts
    RELIABLE CONNECTIONS - TCP guarantees delivery of data
    PERFORMANCE OPTIMISATION - Includes mechanisms to modify transmission variables depending on network conditions
  115. 115TCP FINITE STATE MACHINE- TCP uses a finite state machine at the end of each connection.
    - Exchanges events between the two ends to drive state transitions.
    - The events are bit flags which are set in the TCP header
  116. 116TCP BIT FLAGSURG - set to 1 if the urgent pointer is in use
    ACK - indicates acknowledgement number is valid
    PSH - data in TCP segment should be sent to application ASAP
    RST - Connection must be reset
    SYN - synchronisation is taking place
    FIN - finish, no more data to be sent
  117. 117TCP HEADERSource Port Number | Dest Port Number
    Sequence Number
    Acknowledgement Number
    HL | Res Field | TCP Flags | Window Size
    TCP Checksum | Urgent Pointer
    TCP Options
    Data Portion of Packet
  118. 118TCP 3 WAY HANDSHAKE step 1STEP 1
    Host A sends a TCP open request with SYN bit set and an initial sequence number of x
    e.g. 167
    Host B Receives the open request.
  119. 119TCP 3 WAY HANDSHAKE step 2STEP 2
    Host B sends back a frame with a sequence number of y e.g. 498
    and acknowledgement number of x+1 e.g. 168
    Host A receives the acknowledgement frame
  120. 120TCP 3 WAY HANDSHAKE step 3STEP 3
    Host A sends back an acknowledgement number of y+1 e.g. 499
    Host B receives the acknowledgement frame
    Connection is now OPEN
  121. 121TCP 3 WAY HANDSHAKE TO CLOSEHost A sends FIN -------> Host B receives FIN
    Host B sends FIN+ACK -----> Host A receives FIN+ACK
    Host A sends ACK -----> Host B receives ACK
    CONNECTION CLOSED
  122. 122UDPUSER DATAGRAM PROTOCOL
    - Provides no guarantees to upper layers on message delivery
    - Stateless, retains no state of UDP messages once sent.
    - Suitable for very large numbers of clients such as streaming apps
    - Good for unidirectional comm e.g. stock
  123. 123UDP PROPERTIESSimple
    No error detection/correction
    No connection-oriented links
    No verification of delivery
  124. 124UDP HEADERSOURCE PORT | DESTINATION PORT
    LENGTH | CHECKSUM
    Source port - assigned by originating host
    Dest port - well known port associated with application
    Length - Indicates length in bytes of entire datagram
    Checksum is optional
  125. 125WELL KNOWN PORTSHTTP - 80 - TCP
    SMTP - 25 - TCP
    ECHO - 7 - TCP/UDP
    TIME - 37 - TCP/UDP
    POP3 - 110 - TCP
    SSH - 22 - TCP
    DNS - 53 - TCP/UDP
  126. 126UDP MULTICAST- Sender creates one packet
    - Receivers join to receive multicast message
    - Specialist routing protocols identify routes
    - Routers duplicate the distribute to all connected receivers
  127. 127UDP MULTICASTTo mitigate unreliability of UDP, data can be sent over 2 channels e.g. A and B
    Their routes have to be geographically diverse.
  128. 128ifconfigEnable/Disable network adapters
    Assign IP address and netmask details
    Show current network interface configuration
  129. 129iwconfigSimilar to ifconfig and ethtool for wireless cards, can also view and set basic wifi network details
  130. 130netstatDisplays active TCP connections and ports on which the computer is listening
    Displays ethernet statistics, the IP routing table and stats for IP, TCP, UDP etc
    Comes with variety of options for displaying properties of network.
  131. 131nslookupCommand-line administrative tool for testing and troubleshooting DNS servers
  132. 132tracerouteUses the TTL field in the IP header to trace the route of a packet. Sends packets with TTL values that gradually increase from packet to packet, starting with TTL value of one.
    Routers decrement TTL values of packets by one when routing and discard packets whose TTL value has reached zero, returning ICMP error message ICMP Time Exceeded

Information

Description
Computer Science Flashcards on Architecture and Networks, created by Jojo O'Gorman on 25/04/2019.
Created by
Jojo O'Gorman
Views
4
Rating

Feedback

What is it about?

What do you think of the new look?

How do you like it?