Flashcards
SLR 1 - Structure and Function of the Processor
Cards in this deck (29)
- 1ALUArithmetic Logic Unit
The part of the CPU where data is processed and manipulated. Also carries out logical comparisons and decisions. Ultimately outputs the result of calculations to the Accumulator. - 2CUControl Unit
The part of the CPU that manages the execution of instructions. The Control Unit fetches each instruction in sequence, and decodes and synchronises it before executing it by sending control signals to other registers, buses or processors. - 3RegistersMemory locations within the processor, very fast speed but cannot store much data. The 5 Registers are: Program Counter, Memory Address Register, Memory Data Register, Accumulator and Current Instruction Register.
- 4Program CounterStores the address of the next instruction
- 5Memory Address RegisterStores the address of the data or instruction that needs to be fetched. Addresses are copied from the Program Counter or an instruction. Connected to the Address Bus, so it can request data from the address.
- 6Memory Data RegisterStores the fetched instruction or data after it has been received. Connected to the data bus so it can receive data from the memory.
- 7AccumulatorStores the result of calculations from the ALU. Stores the data currently being processed by the CPU.
- 8Current Instruction RegisterStores the instruction which is currently being decoded or executed.
- 9The 3 Buses and what they doAddress Bus: Carries addresses from the MAR to be fetched from the memory and is one way.
Data Bus: Carries data and instructions to and from the processor and is bidirectional.
Control Bus: Allows the CPU to communicate with other devices around the computer, allows the CPU to carry out instructions in order to control the computer and is bidirectional. - 10The Process of FetchProgram counter contains address of next instruction which is sent to MAR
MAR stores the next data or instruction to be fetched
Address is sent via the address bus to fetch the data or instruction
Data or instruction is carried back across the data bus and stored in MDR
Program Counter increments - 11The Process of DecodeDecoded by Decode Unit in Current Instruction Register by splitting into Opcode and Operand
- 12OpcodeThe first 4 bits of the instruction. Represents the command.
- 13OperandThe last 4 bits of the instruction.
Represents the address if needed. - 14The Process of ExecuteCarries out the decoded instructions
CPU fetches any data which needs to be fetched for the instruction
ALU does any calculations - 15Central Processing UnitMain part of a computer consisting of the registers, ALU and Control Unit
- 16ClockspeedNumber of pulses the internal clock generates in a second. Controls the speed of the CPU. Measures in Hertz, which is number of cycles (Fetch, Decode, Execute) per second. More cycles means more instructions carries out per second. More Hertz means the CPU heats up more and must be cooled to be sustained. CPUs have a max speed they can reach before they are destroyed.
- 17CacheMDR can only hold one value, so the Cache is a small piece of memory which stores any instructions used multiple times. This speeds up the CPU as it eliminates the fetching of the same instruction multiple times. Cache is small but fast memory which is close to the CPU.
- 18CoresMultiple processors which work together. They work at the same time so more instructions can be carried out in a single cycle.
- 19Size of RegistersBigger registers means more data can be processed at once.
- 20Size of the Data BusBigger buses means more data can be transferred at once, leading to faster reading and writing.
- 21Size of RAMA bigger RAM becomes full less often, meaning Virtual Memory does not have to be used as much. Virtual Memory is slower than RAM as it is stored in a slower and further away hard disc.
- 22PipeliningProcessors work in cycles, so pipelining is when multiple steps of a process are carried out at once. For example in a CPU this is when Fetching, Decoding and Executing are all happening at once. It still follow the Fetch-Decode-Execute pattern but when one instruction begins to be decoded, the next instruction is fetched.
- 23Limitations of PipeliningPipelining can only be used when subsequence instructions can be predicted as it pre-fills the instructions for separate cores.
- 24Flushing the PipeWhen the predicted instructions are removed and the right instructions replace them, for example after a branch.
- 25Benefits of PipeliningPipelining increases the clock speed as more Fetch-Decode-Execute cycles can be completed per second, however this will make the CPU overheat and require cooling.
- 26Von Neumann ArchitectureInstructions and data share the same memory space and are served by one set of buses. These are collectively known as the System Bus, and can't tell the difference between instructions and data in binary. Single Control Unit or processor means only one cycle can be completed at a time.
- 27Harvard ArchitectureInstructions and data have separate memory units or areas in memory. Each has their own set of buses. The next instruction can be fetched while the current one is executed. Used by RISC Processors.
- 28Distributed ComputingEach computer on a network takes on part of a problem. They send the result to the main computer. Some problems may be faster, some may be slower. Better at executing complex multi-step commands.
- 29Contemporary ArchitectureAny modern set of disciplines that describes the function, organisation and implementation of a computer system.
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- AS level Computing Flashcards on SLR 1 - Structure and Function of the Processor, created by Kyle Clinch on 13/01/2020.
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