Flashcards
Week 1: Integer representation, MIPS architecture & assembly
Cards in this deck (19)
- 1Place value system- Each digit is worth a value depending on its position in a number
- Base of number system = ratio between adjacent columns
- Trade-off between smaller bases (less compact, simple range of digits) and higher bases (more compact, wide range of digits) - 2Unsigned integers: binary- 2^N values in N bits
- Range of unsigned integers we can present in N bits is 0 to 2^N - 1 - 3Unsigned integers: hexadecimal- Base 16: digits 0-9, A-F
- Convenient shorthand for writing binary - 4Representing signed integers- Use one of the bits to store the sign
- Largest signed integer we can represent in N bits is roughly half the largest unsigned integer
- 3 representation methods: signed magnitude, Two's complement
and excess-k - 5Signed magnitude representation- Most significant bit (MSB) stores the sign
- Rest store the absolute value (magnitude)
- Includes +0 and -0
- Range of signed integers we can represent in N bits is -(2^(N-1) - 1) to 2^(N-1) - 1 - 6Adding in signed magnitude
- 7Two's complement representation- For N bits, -M is represented as 2^N - M
- Range of signed integers we can represent in N bits is -2^(N-1) to 2^(N-1)-1
- Includes only +0
- To convert from Two's complement to decimal, give the MSB a negative weight
- To negate, flip all its bits and add 1 - 8Von Neumann architecture: 3 main components1. Memory - stores data and instructions
2. Control Processing Unit (CPU) - contains Arithmetic/Logic Unit (ALU),
registers and control
3. Input/Output (I/O) - 9MIPS: General Purpose Registers (GPRs)- Store temporary results
- 32 registers, each 32 bits in size
- Fast but expensive memory
- Physically located on CPU chip
- Prefixed with $ in assembly language - 10MIPS: Arithmetic Logic Unit (ALU)Performs computations on register and integer values (not main memory)
- 11MIPS: Special Purpose Registers- PC (Program Counter) - holds address of instruction currently being executed
- HI, LO - for multiplication/division results
- IR (Instruction Register) - stores 4-byte instruction currently being executed
- MAR/MRR/MWR (Memory Address/Read/Write Register) - 12Fetch-decode-execute cycle1. Fetch next instruction from memory (PC) and place in IR
2. Decode instruction in IR to detremine type
3. Execute instruction
4. Go to next instruction (+ 4 bytes) - 13Load-store architecture- Programs and data live in main memory (not on CPU chip)
- Load data into register to work on it; store back into memory when done
- Memory addresses are 32 bits long and unsigned - 14MIPS memory: text segment- Executable code goes here
- PC register value is a CPU "pointer" to the text segment - 15MIPS memory: data segment- For static and globally available data
- Values change but size does not (size is known at compile-time)
- E.g. literal strings in source code (e.g. "Hello World"), global variables - 16MIPS memory: heap segment- Technically part of data segment
- Contains all dynamically-allocated memory (i.e. allocated during execution)
- All Python objects and their instance variables
- Grows "downwards" as memory is allocated and shrinks when deallocated - 17MIPS memory: stack segment- Contains system stack
- Temporary storage of function information and saved register values
- Grows "upwards" towards heap - 18Assembler directives- Don't assemble to machine language instructions (only interpreted by the assembler)
- Functions: to allocate space/data, to switch modes - 19Dealing with immediate values- Immediates must be in 32-bit format to go into ALU
- Use zero extension for andi, ori, xori
- Use sign extension for addi, sll, srl, sra, slti
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- Computer Science (FIT1008: Intro to Computer Science) Flashcards on Week 1: Integer representation, MIPS architecture & assembly, created by Melina Mackey on 25/04/2020.
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- Melina Mackey
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