Flashcards
Module 15
Cards in this deck (11)
- 1EXPLAIN SODIMM?SMALL OUTLINE DUAL INLINE MEMORY MODULE(SODIMM):
- a memory chip that is smaller than what you might find in a desktop system(commonly used in laptops, notebooks, or over limited systems)
- chip dimensions or generally consistent, however, the notch placement at the bottom varies with the type
- easily replaceable and upgradeable provided the specifications are compatible
SODIMM CHARACTERISTICS:
- the smaller size generally has no impact on performance compared to physically larger memory chips
- many variants and specifications(primarily in clock speed and pin configuration). Will find variations in what's known as the data rate(DR):
SDR = single data rate
DDR - double data rate
And then, DDR2, DDR3, DDR4 - 2EXPLAIN SDRAM?SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY:
- refers to a performance characteristic, not the physical chip
- almost all modern systems are using some form of SDRAM
- It means clock speed is determined by the system bus speed, not the chip itself
- most commonly implemented as a 168 pin DIMM for SDR(has two notches at the bottom) and 184 pins for DDR(has one notch). So not compatible with each other, you had to use the appropriate type of chip
SDRAM CHARACTERISTICS:
- was the successor to asynchronous DRAM with the chip having its own clock signal, standard since the mid to late 1990s
- the synchronous aspect of the clock cycle allows for greater concurrency of operations and higher data transfer rates than asynchronous
- initial implementation transferred data once per cycle (single date rate or SDR) -superseded by double data rate (DDR), which transferred data twice per cycle - 3EXPLAIN DDR2?Double Data Rate 2 (DDR2)
- a form of synchronous dynamic RAM(SDRAM)
- it's twice the speed of DDR
- most commonly implemented as a 243-pin DIMM or a 200-pin SODIMM
- not compatible with original DDR(notch at the bottom won't fit into the same slot)
DDR2 CHARACTERISTICS:
- implements variations in the clock speed to essentially adjust dynamically to still improve the rate at which data is transferred
- can use DDR2 with a bus clock speed between 200 and 533 MHz
- bandwidth between 3200 and 8533 MB/S(a lot of data)
- as with DDR, DDR2 also transfers data twice per clock cycle
- but the clock speed of the chip itself is half that of the bus clock speed, hence the chip would cycle twice per bus cycle, making it twice as fast as the original DDR(four pieces of data ready to be transferred)
- an MT/S value(million transfers per second) is often included when referring to the chip(eg. DDR2-800 = 800 million transfers per second(higher it is, faster the overall chip will be) - 4EXPLAIN DDR3?DDR3:
- A form of SDRAM
- Twice the speed of DDR2
- Most commonly implemented as a 240-pin DIMM or a 204-pin SODIMM
- Not compatible with original DDR or DDR2
DDR3 CHARACTERISTICS:
- bus clock speed of between 400 & 1066 MHz
- Bandwidth between 6400 & 17066 MB/s
- As with DDR2, DDR3 also transfers data twice per clock cycle
- The clock speed of the chip itself is one quarter that of the bus clock speed, hence the chip would slow down & cycle four times per bus cycle, making it twice as fast as DDR2
- An MT/s value(million transfers per second) is often included when referring to the chip(e.g. DDR3-1600 = 1600 million transfers per second) - 5EXPLAIN DDR3?DDR4:
- A form of SDRAM
- Twice the speed of DDR3
- Currently the most recent variant of DDR
- Commonly implemented as a 288-pin DIMM or a 256-pin SODIMM
- Not backward compatible with original DDR, DDR2 or DDR3
DDR4 CHARACTERISTICS:
- bus clock speed between 1066 and 2133 MHz
- bandwidth between 6400 and 17066 MB/s
- as with DDR3, DDR4 also transfers data twice per clock cycle
- the clock speed of the chip itself was 1/8 of the bus clock speed, hence the chip would cycle eight times per bus cycle, making it 2x as fast as DDR 3
- an MT/s value (million transfers per second) is often included when referring to the chip(eg. DDR4-3200 = 3200 million transfers per second)
Physical Chip Comparison:
DDR - notch slightly off-center
DDR2 - notch closer to center
DDR3 - notch noticeably off-center
DDR4 - notch slightly off-center
- despite any physical similarities, none of the DDR memory types are compatible with each other, nor should they fit in slots not designed for their type(hence need to know what type of DDR memory your system is using if replacing, upgrading, or adding new chips - 6EXPLAIN SINGLE CHANNEL? (CHANNELS FOR MEMORY)SINGLE CHANNEL RAM:
- data flows between the processor and RAM via pathways known as the memory bus
- for modern systems, a single physical RAM chip operates over a 64-bit memory bus or channel
- if your system has only one channel and there are two physical chips, they share the same channel(e.g physical chip DIMM1 and DIMM2 both operate on channel A)
- so the bus itself is collectively made up of 3 pathways(1 for data transfer, 1 to control it, address of where data resides in any physical chip)
- when using single-channel RAM, regardless of the number of physical chips, all chips must share the single-channel when communicating with the processor
- all available memory will be addressed separately so there are no conflicts in address space, but no operations can be performed simultaneously over the same channel(eg. if you have two different sets of data in each chip you cannot access that data at the same time) - 7EXPLAIN DUAL CHANNEL? (CHANNELS FOR MEMORY)DUAL CHANNEL RAM:
- implement two separate dedicated buses of 64 bits each
- so if there are two physical chips, they each have their own channel
- likely you would have four physical chips, so they can operate in pairs(2 in channel A & 2 in channel B)
- if you only have two chips however you should place one of them in channel A and the other one in channel B, so now you can address either chip separately on its own channel and simultaneously so that you can improve the performance
- with dual-channel memory, the effective bus width is 128 bits
- when using dual-channel RAM, if there are only two physical chips, then each one operates on its own channel when communicating with the processor
- all available memory is still addressed separately so there are no conflicts in address space, but operations can now be performed simultaneously over each channel, allowing you to improve the performance by multitasking access to your memory - 8EXPLAIN DUAL CHANNEL? (CHANNELS FOR MEMORY)TRIPLE CHANNEL RAM:
- implement three separate dedicated buses of 64 bit each
- if there are three physical chips, they each have their own channel(each channel usually supports two physical DIMMS)
- if there are six physical chips, they can operate in pairs(sharing the channels)
- with triple channel memory the effective bus width is 192 bits
- when using triple channel or RAM, if there are only three physical chips, then each one operates on its own channel when communicating with the processor
- all available memory is still addressed separately so there are no conflicts in address space, but operations can now be performed simultaneously over each channel - 9EXPLAIN ERROR CHECKING & CORRECTING(ECC) MEMORY?ECC MEMORY
- a feature of memory
- a method for discovering and correcting single-bit memory errors
- more reliable than NON-ECC memory, but requires more processing (slower)
- used when the integrity of the data is more important than the speed of processing
- visibly identifiable by the ninth module on the chip(black subchips, 8 on NON-ECC memory) - 10EXPLAIN THE ERROR-CORRECTING METHOD?ERROR CORRECTING:
- in terms of error correction it uses a method known as parity
- idea is that for every 8 bits written(1 byte), a 9th parity bit is also stored, hence 9 modules on the chip
- for each byte, the total number of 1's is summed by parity(Even parity = if the answer is an even number of 1's(parity bit(9th bit) is set to 0), Odd parity = if the answer is an odd number of 1's (parity bit set to 1))
- when that same data is subsequently read, the value of the parity bit is compared to the actual data
- if the parity bit matches the bit count, data is assumed to be correct
- if the parity bit value doesn't match the big count(e.g. four 1's(even number) but the parity bit is set to 1, not 0) the data is assumed to be corrupt
- error correcting memory will attempt a repair using algorithms that were generated when the data was originally written to identify which bits are in error and correct it
- limited to single-bit errors within each byte
- less common in modern systems as the reliability of hardware has increased, as have other methods of using data integrity checks - 11PARITY VS NON-PARITY MEMORY?- this is a method for discovering single-bit memory errors
- not as effective as ECC memory as errors are only detected, not connected
- generally causes a stop error in the system, with any changes to data being lost(better to lose corrupt data than to store it)
- parity chip has nine modules compared to the non-parity chip which had eight
PARITY vs NON-PARITY:
- was a predecessor to ECC memory
- common in early memory chips that used high voltages, resulting in higher operating temperatures
- hence read/write errors are more common due to the higher temperatures
- uses the same even/odd parity mechanism as ECC memory, but limited to detection only
ultimately parity memory was a little more reliable than non-parity memory
Information
- Description
- Learning Technology Specialist CompTIA A+ (Core 1) Flashcards on Module 15, created by Chantelle Knight on 11/09/2021.
- Created by
- Chantelle Knight
- Views
- 1
- Rating