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CoCs Final Exam Review

Jacob Karvelis Computer Science English 39 cards

Draw a diagram for a 4 bit register file, containing 4 registers

Cards in this deck (39)

  1. 1Draw a diagram for a 4 bit register file, containing 4 registersA decoder is used to select which register to write to, the output of which is fed into the 'load' of the correlating register. This decoder has a 'write' enable input. A WD (write data) input is send to the 'in' of each register, this is the data to write. The output of each register is split into n wires, and the corresponding wire is sent to the nth mux. The output of each of these muxes is collected into the R1 output of the reg file. RA1 is used to select which bit from each mux will be sent through (and thus which reg will be read).
    The included diagram does not include it, but we would actually have 2n muxes, and a RA2 input. The process for building those is the same. Their outputs will go to R2    Draw a diagram for a 4 bit register file, containing 4 registers
  2. 2Draw a block diagram for a MIPS register fileDraw a block diagram for a MIPS register file
  3. 3How many wires are required to make a regfile circuit?32^2 if you are clever. 32^3 if you aren't
  4. 4Control UnitWhat to do, What data to do it to, and When to do it.
    This information comes from the instruction primarily.
  5. 5Data PathUse, Store, and Manipulate user data
  6. 6Create the Data Path for this simplified Register Transfer Language: A <- B+A C<-B B<-A-B Mem[A] <- BCreate the Data Path for this simplified Register Transfer Language: A <- B+A C<-B B<-A-B Mem[A] <- B
  7. 7Given the state diagram and register transfer language from class, draw the control unit for the multi cycle cpuCheck your notes / online for the answer to this one
  8. 8Now go do the Single Cycle and Multi Cycle worksheets on the website: https://cs.rit.edu/~paw/20231.250.html#homework I'll bet there will be questions like this.Answers are there too
  9. 9What is the execution time formula?Instruction Count (IC) * Cyles Per Instruction (CPI) * Clock Cycle Time (CCT)
  10. 10How does a RISC ISA affect the execution time formula?IC goes up, because each instruction only does a little work, so you need more instructions to do a lot of work. CPI Goes down because each instruction does only a little work and thus has few sequential steps. CCT is unaffected by the ISA alone.
  11. 11How does a CISC ISA affect the execution time formula?IC goes down because some instruction do a lot of work, so instructions needed to do a lot of work decreases. CPI goes up because since some instructions do a lot of work they have many sequential steps. CCT is unaffected by the ISA alone
  12. 12Why is VAX ISA faster than a naive implementation of MIPS ISA?there is a lot of time in MIPS wasted in setup, tens of thousands of cycles. VAX only has to do setup once. Thus even though the instructions are bulkier, it can be faster.
  13. 13How can RISC ISA's become faster than CISC ISAsPipelining, we reduce setup time significantly and increase hardware utilization
  14. 14What is pipelining?Pipelining is the idea of increasing the bandwidth of your CPU so as to increase utilization of the hardware and decrease the amount of time wasted on setup.
  15. 15What is the Ideal Pipeline CPI?1
  16. 16What is the Ideal Pipeline Speedup?Number of stages times speedup
  17. 17When does the ideal pipeline speedup occur?When the lengths of all stages are equal
  18. 18How do we get closer to our ideal pipeline CPI/Speedup?Split up the hardware/introduce more. This way we can reduce the time any 1 stage takes to try to get the speed of the stages closer to equal.
  19. 19Why does splitting up hardware for pipelining eventually reach a limit?The time taken to move electrons around eventually dominates the timing. It also creates a lot of heat.
  20. 20What is a pipeline hazard?A problem that arises when execution overlap occurs, IE when in the steady state hardware is being used when another stage needs it
  21. 21What is the simplest solution to a pipeline hazard?A stall - just insert a waiting time until the hardware is free
  22. 22What is the real pipeline CPI?1 + (number of stalls)/IC
  23. 23What is a structural hazard?A problem where the hardware cannot support the overlapping execution that is occurring.
  24. 24What is a control hazard?The idea that we always must know the next program counter for every cycle, but for branches/jumps, we don't know it
  25. 25What is the biggest issue in pipelining?Control hazards
  26. 26Which 3 questions must be answered to solve a control hazard/1) is this a branch/jump instruction
    2) should we take the branch / jump
    3) What is the destination
  27. 27What is the good way to solve structural hazards?Duplicate the hardware that we are unable to use in the overlapping execution
  28. 28What simple strategy will solve any pipeline hazard?Stalling.
  29. 29What is a pipeline registerA register added to the data path to pass information along to each stage, because it is needed every cycle when pipelining.
  30. 30What is the best solution we currently have to control hazards?Branch Prediction.
    Predict whether we will or won't take a branch, which we can then use to answer the other two questions and get left with at most 1 extra cycle per branch instruction.
  31. 31What is a data hazard?A hazard that arises when the instruction in the pipeline requires the result of another instruction currently in the pipeline. We would have to wait for the pipeline to complete.
  32. 32What is the primary method of bypassing data hazards?Forwarding/Bypassing: retrieving the missing element from an internal buffer, rather than waiting for the completion of the writeback phase.
  33. 33Temporal LocalityIf a data location is referenced, it is likely to be referenced again soon
  34. 34Spatial LocalityIf a data location is referenced, nearby locations are likely to be referenced soon
  35. 35Block/LineThe minimum unit of information present/not in a cache
  36. 36Hit RateFraction of memory accesses actually contained in a level of the memory hierarchy
  37. 37Miss RateFraction of memory accesses not found in a level of the memory hierarchy
  38. 38Hit TimeThe time required to access a level of the memory hierarchy, including the time needed to determine if it was a hit
  39. 39Miss TimeThe time it takes to fetch a block from a lower to higher spot in the memory hierarchy, including the time to transmit the block, transmit it between levels, insert it into the level that experienced the miss, and pass in the block to the requester.

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Computer Science Flashcards on CoCs Final Exam Review, created by Jacob Karvelis on 10/12/2023.
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Jacob Karvelis
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