Flashcards
FPGA vs. Processor, ARM Cortex M - Lecture 3
Cards in this deck (10)
- 1State the differences between a FPGA and ProcessorFPGA
(computing in space)
• Parallel execution
• Configurable in 102
-103 cycles
• Fine-grained data
• Application specific operators
• Large area (switches, SRAM)
• Entire applications don’t fit
• Slow synthesis, P&R tools
Processor
(computing in time)
• Sequential execution
• Programmable every cycle
• Fixed-size operands
• Basic operators (ALU)
• Compact
• Handles complex control
flow
• Fast compilers - 2In FPGAs is it better a Hard or a Soft Processor?Hard Processors:
• Made of transistors
• Small, fast, power
efficient but not very
flexible
Soft Processor:
• Use the FPGA fabric
• HDL source code (eg.
VHDL)
• Configured onto chip just
like another circuit - 3State some of the configurable option of a soft core processor• Datapath units
• Cache
• Bus architecture - 4State some of the specification of the ARM Cortex-M0 processorConfigurable, 3-stage pipeline, 32-
bit RISC processor.
• 3-stage pipeline : fetch-decodeexecute
• Datapath is 32 bit wide.
• 16 general purpose registers, loadstore
architecture.
• 12 Kgates, 0.9 DMIPS/MHz and 56
instructions.
• Thumb-2 instruction set combines
high-code density with 32-bit
performance (most ARMs
implement 16-bit and 32-bit
instructions). - 5How many instructions include the instruction st of ARM6MJust 56 instructions, all with guaranteed execution time
- 6How many bytes occupy the instructions?2 bytes of memory
- 7State how many clock cycles need the instructions to execute for add,shift, logical OR and also for data transfers and branchesWhen executed, complete in a fixed time–Data processing (e.g. add,
shift, logical OR) take 1 cycle–
• Data transfers (e.g. load, store) take 2 cycles
• Branches, when taken, take 3 cycles
• The instructions operate on 32-bit data values–Processor registers and
ALU are 32-bit wide! - 8State the pipeline stages• Fetch:
The instruction is fetched from memory and placed in the instruction
pipeline
• Decode:
The instruction is decoded and the datapath control signals prepared
for the next cycle
• Execute:
The register bank is read, an operand shifted, the ALU result
generated and written back into destination register - 9State the registers of Cortex-M0 fAll registers are 32-bit wide
13 general purpose registers
Registers r0 –r7 (Low registers)
Registers r8 –r12 (High registers)
3 registers with special
meaning/usage
Stack Pointer (SP) –r13
Link Register (LR) –r14
Program Counter (PC) –r15
Special-purpose registers -xPSR
Cortex- - 10Explain what is thumb technologyARM introduced Thumb technology to reduce the memory footprint of
applications but also reduces the amount of instruction fetches from external
memory.
Information
- Description
- Electronics (Embedded System) Flashcards on FPGA vs. Processor, ARM Cortex M - Lecture 3, created by Konstantinos Athanasiou on 06/10/2016.
- Created by
- Konstantinos Athanasiou
- Views
- 1
- Rating