Mind map
Truth table and inputs/outputs
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Truth table and inputs/outputs
Use decoder4to16 (form by two chip74LS138)
- Transform into a vhdl file with 4 inputs, 16 outputs and 3 Enables
- Adequate to our parameters
- ispLEVER, to compile all together
- ActiveHDL to simulate the results
- Adequate to our circuit_1
- Repeat the process
- Adequate to our circuit_1
- Synplify to discover our new circuit designed
- ActiveHDL to simulate the results
- ispLEVER, to compile all together
- Adequate to our parameters
- Transform into a vhdl file with 4 inputs, 16 outputs and 3 Enables
Information
- Description
- CSD project_1 (EX1A)
- Created by
- cristinaaa.perez
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- 5
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- History
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- Created by Cristina Pérez9355 · Oct 27, 2015
- Copied by cristinaaa.perez · Oct 27, 2015
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