STRUCTURE & FUNCTION OF THE PROCESSOR 1.1.1

STRUCTURE & FUNCTION OF THE PROCESSOR 1.1.1

1. ARITHMETIC & LOGIC UNIT (ALU)

   • carries out the calculations & logical decisions
   • results of its calculations are stored in the accumulator

2. CONTROL UNIT (CU)

   • controls how data moves around parts of the CPU & how it moves between the CPU & memory
   • sends out signals to co-ordinate how the processor works
   • instructions are decoded here

3. BUSES

   • DATA BUS
     • carries data between the processor & memory
     • direction is dictated by how data is transferred in & out of the processor & the other components
   • buses are the communications channels through which data can be sent around the computer
   • ADDRESS BUS
     • carries the address of the memory location being read from or written to
     • always in one direction from processor to other components
   • CONTROL BUS
     • sends control signals from/to the CU to/from the other components
     • always in two directions

4. SPECIAL-PURPOSE REGISTERS

   • PROGRAM COUNTER (PC)
     • this is automatically incremented as each instruction is executed
     • used by the processor to hold the address of the next instruction
   • ACCUMULATOR (ACC)
     • the increment of values occur in the ACC for programming calculations
     • temporary memory location that stores values of all AL calculations being carried out by the cpu
   • MEMORY ADDRESS REGISTER (MAR)
     • holds the address of data & instructions that are to be fetched from or sent to
     • used to access data & instructions from memory address during the execution phase of an instruction
   • a register is a special memory location that allows very fast access
   • MEMORY DATA REGISTER (MDR)
     • stores the data that has been fetched from or stored in memory
   • CURRENT INSTRUCTION REGISTER (CIR)
     • holds the current instruction to be executed, having been fetched from memory
   • works at very fast speeds & are close to cu
     • means that there is no delay

5. CENTRAL PROCESSING UNIT (CPU)

   • carries out all the instructions in a computer
   • made up of billions of transistors
   • the clock speed at which it works is measured in Gigahertz
   • works by fetching, decoding & executing instructions
   • consists of ALU, CU, registers & buses
   • IMPROVING CPU PERFORMANCE
     • MULTIPLE CORES
       • each core is a distinct processing unit on the CPU
       • when multi-tasking, different cores can run different applications
       • it is also possible for multiple cores to work on the same problem
     • CACHE MEMORY
       • small amount of fast memory built into the processor - so it is faster than using main memory
       • the larger the cache the slower it operates
       • by anticipating the data & instructions that are likely to be regularly accessed & keeping these in cache memory, the overall speed at which the processor operates can be increased

6. FETCH-DECODE-EXECUTE CYCLE

   • MAR <------- [PC] PC    <------- [PC] + 1; //MDR <------- [MEMORY]addressed CIR   <------- [MDR] [CIR] decoded & executed
   • STEPS OF THE FETCH PHASE:
     • 1. address of next instruction to be executed is copied to MAR
     • 2. instruction held at that address is placed in MDR
     • 3. simultaneously, contents of PC are incremented by 1 to get ready for next instruction
     • 4. contents of MDR are copied to CIR <- this frees up MDR for the execute phase
   • STEPS OF THE EXECUTE PHASE
     • 1. instruction held in CIR is decoded by instruction decoder
     • 2. opcode identifies type of instruction it is & the relevant part of CPU/processor executes the instruction

7. VON NEUMANN ARCHITECTURE

   • to allow communication between processes there is a bus on which messages can be sent - known as VNA
   • follow the fetch-decode-execute cycle
   • uses a single CU
   • stores data & instructions in the same memory
   • instructions are executed in a linear sequence

8. HARVARD ARCHITECTURE

   • data & instructions are stored in separate memory units w/ separate buses
   • means that while data is being written to or read from the data memory, the next instruction can be read from the instruction memory (because there are separate buses)
   • tends to be used by RISC processors (1.1.2)