1.1.1 – Structure & Function of the Processor

1.1.1 – Structure & Function of the Processor

1. CPU

   • Four main parts
     • Immediate Access Store
       • Holds instructiosn and data ready to be used by CPU. Set of memory locations. Also called main memory, RAM, primary memory
       • Also used to store results of any processing it does.
       • When an application/file is opened, it is moved form storage on the hard disk to the IAS, ready for the CPU. But when you save work its moved from the IAS back to the storage device.
     • Registers
       • Program Counter
         • Holds address and tracks memory location of next instruction to be fetched and executed
         • Increments with each cycle so it holds next instruction - allows program to be executed in sequence
       • Memory Address Register
         • Holds address to be read to/ written from
       • Memory Data Register
         • Holds data to be read from/written to RAM
       • Current Instruction Register
         • Holds current instruction being executed
       • Accumulator
         • Holds data being worked on and results of ALU
       • Memory locations within processor, storing data and instructions.
       • Status Register
         • Holds info about last operation
         • Hardware register that holds info about state of processor
       • Interrupt Register
         • Holds details about whether an interrupt has happened
       • Stack Point Register
         • Small register that stores address of last program request in a stack.
           • Stack = special buffer that stores data from top down. As new requests come they 'push down' older ones
       • General Purpose Register
         • Discrete memory locations in CPU that hold temp data + instructions
     • Control Unit
       • Sends out signals to coordinate how processor works. Control how data moves around between processor and memory
       • Manages how instructions are executed
       • Controls fetch-decode-execute cyce
         • Fetches instructions and data from memory unit
           • Decodes instruction
             • Executes instruction
     • Arithmetic/Logic Unit
       • Carries out calculations and logical decisions. Results of calculations stored in ACC
       • 3 main functions
         • Performs arithmetic calculations on data
         • Performs logical operations on data
         • Holds data already worked on, ready for processing. All data going in/out of CPU goes in via ALU
   • Buses
     • Data Bus
       • Transfers binary data between stated memory locations
     • Address Bus
       • Carries addresses of memory locations used to store data and instructions between CPU and RAM
     • Control Bus
       • Signals sent along control bus that contorl when things happen
   • Factors affecting CPU performacne
     • Materials
       • Materials CPU is made from affect reliablity, speed and performance
     • Clock Speed
       • How many cycles CPU performes each second
         • Higher clock speed = faster CPU
     • Cores
       • Each core works on separate calculations.
         • More cores = faster (only if software has been written to take advantage of multi-core technology)
     • Cache
       • Faster to read from than RAM
       • Computer puts data here when needs to access it several times
       • More cache = better CPU performance
     • Word Size
       • Number of bits CPU works with
         • More bits it can work with in one cycle = faster CPU

2. Fetch - Decode - Execute Cycle

   • Fetch
     • PC copied to MAR
       • Fetch signal sent across control bus, contents of MAR across address bus
         • Contents of memory location sotred in MAR sent acorss data bus and stored in CIR
           • PC incremented by one
   • Decode
     • Contents of CIR sent to control Unit
       • Control unit decodes instructions
   • Execute
     • Registers changed in different ways during on execution phase, depening on instructions
       • If memory location is to be read form/ written to (LDA or STA) thwn address stored in instructio will be loaded into MAR.
         • When STA - data stored in ACC sent to memory
         • When memory - loaded from memory into ACC
       • If instruction to be carried out (ADD/SUB) then contents of MDR and ACC sent to ALU and result sent bck to ACC

3. Architecture

   • Von Neumann
     • Single control unit
     • Works sequentially through instructions
     • Stores instructions and data together in same memory
   • Harvard
     • Separate memory unit for data and instructions and separate buses
       • Potentially increases speed of processor compared to Von Neumann as buses are separate so don't conflict
     • Pipling
       • Instruction fetched then whilst its being decoded another is fetched and while that is being decoded the first is executed etc
       • Problems
         • Timings
           • Each instruction doesn't take the same amount of time to process so each stage in each pipe might need to start/finish at different times.
             • Solution - 'synchronous' approach
               • Each stage assumed to take fixed number of clock cycles. Next stage in cycle is started when number of cycles passed. This is simpler but less efficient
         • Data hazards
           • Two instructions in a pipe could reference same data so pipelining process must ensure later instructions doesn't access data before earlier
         • Interrupts
           • Interrupts happen in muddle of cycle for some instructions so registers and stages of instructions in pipeline saved.
         • Branching
           • Process next instruction in both possible branches, then when its clear what is needed, one that is not needed is abandoned and pipe flushed out so it can use other instruction in correct branch