OCR AS Computing - Characteristics of Processors

OCR AS Computing - Characteristics of Processors

1. Structure Of A Processor

   • Arithmetic Logic Unit
     • Accumulator
       • The place in which all calculations occur.
     • Memory Data Register
       • Temporarily stores data read from or written to RAM.
     • Performs arithmetic and logical operations on data (e.g. ADD, SUBTRACT)
   • Control Unit
     • Current Instruction Register
       • Holds the current instruction being executed
       • Divided into opcode and operands
     • Memory Address Register
       • Holds the address of the memory location from which data/instructions are to be fetched or written to
     • Program Counter
       • Holds the address of the next instruction to be executed
     • Coordinates activity of a CPU, directing the flow between the CPU and other devices.
   • Buses
     • A set of parallel wires connecting two or more components of a computer.
       • Usually consisting of 8, 16, 32 or 64 lines.
     • Control Bus
       • Bi-directional
       • Transmits commands, timings and status information between system components
       • Control Lines
         • System clock
           • Used to synchronise operations
         • Memory read/write
           • Causes data to be taken from and added to the data bus.
         • Interrupt requests
           • To indicate that a device needs access to the CPU
         • Bus Request/Grant
           • Indicates that a device requests use of a data bus/ CPU has granted access
     • Address Bus
       • Transmits the memory address of words that are used as operands in program instructions so that it can be returned to the processor.
       • Single direction
     • Data Bus
       • Bi-directional
       • Moves data and instructions between system components

2. Fetch-Decode-Execute Cycle

   • The sequence by which an instruction is executed
   • The address of the next instruction is copied from the PC to the MAR
     • That instruction is copied to the MDR, and the PC increments to hold the next instruction
       • The contents of the MDR are copied into the CIR
         • The instruction in the CIR is decoded, using opcodes and operands. The operand can hold:
           • The opcode is used to determine the type of instruction and what hardware to use to execute it
           • The address of the data to be used in the operation (copied to the MAR)
           • The actual data to be operated on, copied to MDR
           • The data to be operated on, which is passed to the ALU
           • Value of address required is copied to the MDR
             • Value in MDR is operated on by the accumulator

3. CPU Performance

   • Cores
     • Multiple cores can operate on different instructions at the same time
   • Clock Speed
     • A greater clock speed results in faster execution of instructions
   • Cache Memory
     • Fetched instructions are copied to cache, if they are needed again, hence more cache means more frequently used instructions can be stored.
   • RAM
     • More RAM means more of the OS can be loaded from storage
       • Less of the OS needs to be swapped when the computer is running.
   • Buses
     • Wider buses allow more data to be transferred at any given rate

4. Architectures

   • Von Neumann
     • Uses a stored program concept
     • Same data bus is used to transfer both data and instructions
     • One instruction executed at a time
     • Instructions and data stored as binary
   • Harvard
     • Data and instructions are stored separately and have individual buses
     • Faster as data and instructions can be fetched in parallel
     • Programs tend to be larger
   • Contemporary
     • SIMD
       • Single instruction, multiple data
       • Several processors can process a large set of data one instruction at a time
       • Used by graphics processors
     • MIMD
       • Multiple instructions, multiple data
       • Different processors may execute different instructions on different pieces of data at any given time
       • Used in design, manufacturing, simulations etc..

5. CISC vs RISC

   • Reduced Instruction Set Computer
     • Each instruction only takes on clock cycle
     • Compiler has to do more work to translate high level programming into machine code
       • Speed is not impacted, as pipelining is possible due to each instruction only taking one clock cycle
         • Used in Harvard architectures
     • Less energy required to power as less complex circuitry
   • Complex Instruction Set Computer
     • More instructions available
       • Better with more intensive tasks
     • Can use compilation to translate a function into a single line of machine code
       • Single line of machine code may take several cycles to execute
     • More complex hardware required
       • More silicon required, more expensive to produce
     • Allows the use of simpler higher level languages
       • Shorter code means little RAM is required to store instructions

6. Multicore and Parallel Systems

   • Distributes workload amongst multiple processor cores, achieving significantly higher performance
   • Amount of increased performance depends on a software's ability to make use of the parallel processing capabilities