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Embarqué Chap2
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- 1What is ARM Architecture?ARM architecture is a family of RISC-based processor architectures
*Well-known for its power efficiency;
Hence widely used in mobile devices, such as smartphones and tablets
*Designed and licensed to a wide eco-system by ARM - 2What's ARM Holdings?*The company designs ARM-based processors;
*Does not manufacture, but licenses designs to semiconductor partners who add their own Intellectual Property (IP) on top of ARM’s IP, fabricate and sell to customers;
*Also offer other IP apart from processors, such as physical IPs, interconnect IPs, graphics cores, and development tools. - 3What are the different ARM Processor Families?*Cortex-A series (Application)
-High performance processors capable of full Operating System (OS) support;
-Applications include smartphones, digital TV, smart books, home gateways
*Cortex-R series (Real-time)
-High performance for real-time applications;
-High reliability
-Applications include automotive braking system ( systèmes de freinage ), powertrains etc.
*Cortex-M series (Microcontroller)
-Cost-sensitive solutions for deterministic microcontroller applications;
-Applications include microcontrollers, mixed signal devices, smart sensors, automotive body electronics and airbags;
*SecurCore series
-High security applications. - 4How to design an ARM-based SoC?1/Select a set of IP cores from ARM and/or other third-party IP vendors
2/Integrate IP cores into a single chip design
3/Give design to semiconductor foundries for chip fabrication - 5ARM Cortex-M Series?*Cortex-M series: Cortex-M0, M0+, M1, M3, M4.
*Energy-efficiency: Lower energy cost, longer battery life
Smaller code: Lower silicon costs
Ease of use : Faster software development and reuse
Embedded applications: Smart metering, human interface devices, automotive and industrial control systems, white goods, consumer products and medical instrumentation - 6ARM Processors vs. ARM ArchitecturesARM architecture
Describes the details of instruction set, programmer’s model, exception model, and memory map
Documented in the Architecture Reference Manual
ARM processor
Developed using one of the ARM architectures
More implementation details, such as timing information
Documented in processor’s Technical Reference Manual - 7Cortex-M4 Processor OverviewCortex-M4 Processor
*Introduced in 2010
*Designed with a large variety of highly efficient signal processing features
*Features extended single-cycle multiply accumulate instructions, optimized SIMD arithmetic, saturating arithmetic and an optional Floating Point Unit.
*High Performance Efficiency: 1.25 DMIPS/MHz (Dhrystone Million Instructions Per Second / MHz) at the order of µWatts / MHz
*Low Power Consumption:Longer battery life – especially critical in mobile products
*Enhanced Determinism: The critical tasks and interrupt routines can be served quickly in a known number of cycles - 8Cortex-M4 Processor Features*32-bit Reduced Instruction Set Computing (RISC) processor
*Harvard architecture:
Separated data bus and instruction bus
*Instruction set:
Include the entire Thumb®-1 (16-bit) and Thumb®-2 (16/ 32-bit) instruction sets
*3-stage + branch speculation pipeline
*Performance efficiency :
1.25 – 1.95 DMIPS/MHz
*Supported Interrupts:
Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
8 to 256 interrupt priority levels
Supports Sleep Modes
Up to 240 Wake-up Interrupts
Integrated WFI (Wait For Interrupt) and WFE (Wait For Event) Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with ARM Power Management Kit
*Enhanced Instructions
Hardware Divide (2-12 Cycles)
Single-Cycle 16, 32-bit MAC, Single-cycle dual 16-bit MAC
8, 16-bit SIMD arithmetic
*Debug
Up to 8 Breakpoints and 4 Watchpoints
*Memory Protection Unit (MPU)
Optional 8 region MPU with sub regions and background region
*Cortex-M4 processor is designed to meet the challenges of low dynamic po - 9Cortex-M4 Block Diagram
- 10Cortex M4 Processor core?Processor core:
Contains internal registers, the ALU, data path, and some control logic
Registers include sixteen 32-bit registers for both general and special usage - 11Cortex M4 Processor pipeline stagesThree-stage pipeline: fetch, decode, and execution
Some instructions may take multiple cycles to execute, in which case the pipeline will be stalled
The pipeline will be flushed if a branch instruction is executed
Up to two instructions can be fetched in one transfer (16-bit instructions) - 12Nested Vectored Interrupt Controller (NVIC)Up to 240 interrupt request signals and a non-maskable interrupt (NMI)
Automatically handles nested interrupts, such as comparing priorities between interrupt requests and the current priority level - 13Wakeup Interrupt Controller (WIC)For low-power applications, the microcontroller can enter sleep mode by shutting down most of the components.
When an interrupt request is detected, the WIC can inform the power management unit to power up the system. - 14Memory Protection Unit (optional)Used to protect memory content, e.g. make some memory regions read-only or preventing user applications from accessing privileged application data
- 15Bus interconnectAllows data transfer to take place on different buses simultaneously
Provides data transfer management, e.g. a write buffer, bit-oriented operations (bit-band)
May include bus bridges (e.g. AHB-to-APB bus bridge) to connect different buses into a network using a single global memory space
Includes the internal bus system, the data path in the processor core, and the AHB LITE interface unit - 16Debug subsystemHandles debug control, program breakpoints, and data watchpoints
When a debug event occurs, it can put the processor core in a halted state, where developers can analyse the status of the processor at that point, such as register values and flags - 17ARM BUSAMBA = ARM Memory Bus Architecture
AHB = ARM High performance Bus
APB = ARM Peripheral Bus
AMBA-AHB connects ARM core with memory, external DRAM
AMBA-APB interfaces ARM core with external low-speed I/O devices using AMBA-APB bridge - 18Cortex-M4 registers*Register bank: Sixteen 32-bit registers (thirteen are used for general-purpose);
*Special registers
-R0 – R12: general purpose registers
-Low registers (R0 – R7) can be accessed by any instruction
-High registers (R8 – R12) sometimes cannot be accessed e.g. by some Thumb (16-bit) instructions
-R13: Stack Pointer (SP)
Records the current address of the stack
Used for saving the context of a program while switching between tasks
Cortex-M4 has two SPs: Main SP, used in applications that require privileged access e.g. OS kernel, and exception handlers, and Process SP, used in base-level application code (when not running an exception handler)
-Program Counter (PC)
-R14: Link Register (LR)
-xPSR, combined Program Status Register - 19-Program Counter (PC)Records the address of the current instruction code
Automatically incremented by 4 at each operation (for 32-bit instruction code), except branching operations
A branching operation, such as function calls, will change the PC to a specific address, meanwhile it saves the current PC to the Link Register (LR) - 20R14: Link Register (LR)The LR is used to store the return address of a subroutine or a function call
The program counter (PC) will load the value from LR after a function is finished
- 21xPSR, combined Program Status RegisterProvides information about program execution and ALU flags
Application PSR (APSR)
Interrupt PSR (IPSR)
Execution PSR (EPSR) - 22APSRN: negative flag – set to one if the result from ALU is negative
Z: zero flag – set to one if the result from ALU is zero
C: carry flag – set to one if an unsigned overflow occurs
V: overflow flag – set to one if a signed overflow occurs
Q: sticky saturation flag – set to one if saturation has occurred in saturating arithmetic instructions, or overflow has occurred in certain multiply instructions - 23IPSRISR number – current executing interrupt service routine number
- 24EPSRThe EPSR contains the Thumb state bit, and the execution state bits for either the:
T: Thumb state – always one since Cortex-M4 only supports the Thumb state
IC/IT: Interrupt-Continuable Instruction (ICI) bit, IF-THEN instruction status bit
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. - 25Memory MapThe Cortex-M4 processor has 4 GB of memory address space
Support for bit-band operation
The 4GB memory space is architecturally defined as a number of regions
Each region is given for recommended usage
Easy for software programmer to port between different devices
Nevertheless, despite of the default memory map, the actual usage of the memory map can also be flexibly defined by the user, except some fixed memory addresses, such as internal private peripheral bus - 26Memory map regions
- 27Code RegionPrimarily used to store program code
Can also be used for data memory
On-chip memory, such as on-chip FLASH - 28SRAM RegionPrimarily used to store data, such as heaps and stacks
Can also be used for program code
On-chip memory; despite its name “SRAM”, the actual device could be SRAM, SDRAM or other types - 29Peripheral RegionPrimarily used for peripherals, such as Advanced High-performance Bus (AHB) or Advanced Peripheral Bus (APB) peripherals
On-chip peripherals - 30External RAM RegionPrimarily used to store large data blocks, or memory caches
Off-chip memory, slower than on-chip SRAM region - 31External Device RegionPrimarily used to map to external devices
Off-chip devices, such as SD card - 32Internal Private Peripheral Bus (PPB)Used inside the processor core for internal control
Within PPB, a special range of memory is defined as System Control Space (SCS)
The Nested Vectored Interrupt Controller (NVIC) is part of SCS - 33Bit-band OperationsBit-band operation allows a single load/store operation to access a single bit in the memory, for example, to change a single bit of one 32-bit data:
Normal operation without bit-band (read-modify-write)
Read the value of 32-bit data
Modify a single bit of the 32-bit value (keep other bits unchanged)
Write the value back to the address
Bit-band operation
Directly write a single bit (0 or 1) to the “bit-band alias address” of the data
Bit-band alias address
Each bit-band alias address is mapped to a real data address
When writing to the bit-band alias address, only a single bit of the data will be changed - 34Bit-band Alias AddressSRAM region
32MB memory space (0x22000000 – 0x23FFFFFF) is used as the bit-band alias region for 1MB data (0x20000000 – 0x200FFFFF)
Peripherals region
32MB memory space (0x42000000 – 0x43FFFFFF) is used as the bit-band alias region for 1MB data (0x40000000 – 0x400FFFFF) - 35Benefits of Bit-Band OperationsFaster bit operations
Fewer instructions
Atomic operation, avoid hazards - 36Cortex-M4 Program ImageThe program image in Cortex-M4 contains
Vector table -- includes the starting addresses of exceptions (vectors) and the value of the main stack point (MSP);
C start-up routine;
Program code – application code and data;
After Reset, the processor:
First reads the initial MSP value;
Then reads the reset vector;
Branches to the start of the programme execution address (reset handler);
Subsequently executes program instructions
C library code – program codes for C library functions. - 37Cortex-M4 EndiannessEndian refers to the order of bytes stored in memory
Big endian: lowest byte of a word-size data is stored in bit 0 to bit 7
Big endian: lowest byte of a word-size data is stored in bit 24 to bit 31
Cortex-M4 supports both little endian and big endian
However, Endianness only exists in the hardware level
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- Engineering Karteikarten am Embarqué Chap2, erstellt von Imen Mahdi am 09/04/2021.
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- Imen Mahdi
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