Computer_Architecture

Computer_Architecture

1. Classes of Computers

   • Personal mobile device (PMD)
     •  a collection of wireless devices with multimedia user interfaces such as cell phones, tablet computers, and so on
   • Desktop
   • Server
   • Clusters/warehousescale computer (WSCs)
     •  Clusters are collections of desktop computers or servers connected by local area networks to act as a single larger computer. Each node runs its own operating system, and nodes communicate using a networking protocol. The largest of the clusters are called warehouse-scale computers 
   • Embedded
     • Embedded computers are found in everyday machines; microwaves, washing machines, most printers, most networking switches, and all cars contain simple embedded microprocessors.

2. CPU

   • application-level parallelism / Parallel computing (pipeline)
     • request-level parallelism (RLP)
       • exploits parallelism among largely decoupled tasks specified by the programmer or the operating system
     • instruction-level parallelism (ILP)
       • pipelining to overlap the execution of instructions and improve performance 
       •  exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
       • dataflow
       • out of order exe
       • VLIM
       • implementation
         • static
           • ILP implemented by compiler before run time
         • dynamic
           • ILP implemented by hardware while run time
       • superscalar CPU
     • data-level parallelism (DLP)
       •  arises because there are many data items that can be operated on at the same time.  is parallelization across multiple processors in parallel computing environments. It focuses on distributing the data across different nodes, which operate on the data in parallel. It can be applied on regular data structures like arrays and matrices by working on each element in parallel. It contrasts to task parallelism as another form of parallelism.
       • vector architectures
         •  exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
       • graphic processor units (GPUs)
       • systolic array processors
       • stream processors
     • task-level parallelism (TLP)
       • arises because tasks of work are created that can operate independently and largely in parallel.  is a form of parallelization of computer code across multiple processors in parallel computing environments. Task parallelism focuses on distributing tasks—concurrently performed by processes or threads—across different processors. In contrast to data parallelism which involves running the same task on different components of data, task parallelism is distinguished by running many different tasks at the same time on the same data
       • thread-level parallelism (TLP)
         •  exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
         • implementation
           • coarse-grained multithreading
             • was invented as an alternative to fine-grained multithreading. Coarse-grained multithreading switches threads only on costly stalls, such as level two or three cache misses.
           • Fine-grained multithreading
             • switches between threads on each clock, causing the execution of instructions from multiple threads to be interleaved. its synchronous execution instructions  in pipeline but some threads may work on parallel by accessing caches, memory and I/O devices
           • Simultaneous multithreading (SMT).
             • The most common implementation of multithreading.  is a variation on finegrained multithreading that arises naturally when fine-grained multithreading is implemented on top of a multiple-issue, dynamically scheduled processor.
         • software models which exploits TLP
           • parallel processing
             •  tightly coupled set of threads collaborating on a single task
           • request-level parallelism
             • execution of multiple, relatively independent processes that may originate from one or more users, which is a form of RLP
     • processor-level parallelism
       • multiple processors works on same task
   • classification by concurrent instruction (or control) streams
     • According to the data transfer mode, computer can be divided into 4 major groups:
     • Single instruction stream, single data stream (SISD)
       • This category is the uniprocessor. The programmer thinks of it as the standard sequential computer, but it can exploit instruction-level parallelism.
     • Single instruction stream, multiple data streams (SIMD)
       • The same instruction is executed by multiple processors using different data streams. SIMD computers exploit data-level parallelism by applying the same operations to multiple items of data in parallel. Each processor has its own data memory (hence the MD of SIMD), but there is a single instruction memory and control processor, which fetches and dispatches instructions.
       • Vector processor / graphics processing units (GPUs).
         •  Instruction operates on multiple data elements in consecutive time steps using the same space
       • Array processor
         •  Instruction operates on multiple data elements at the same time using different spaces
     • Multiple instruction streams, single data stream (MISD)
       • No commercial multiprocessor of this type has been built to date, but it rounds out this simple classification
       • Systolic Array processor
     • Multiple instruction streams, multiple data streams (MIMD)
       • Each processor fetches its own instructions and operates on its own data, and it targets task-level parallelism. In general, MIMD is more flexible than SIMD and thus more generally applicable, but it is inherently more expensive than SIMD. For example, MIMD computers can also exploit data-level parallelism, although the overhead is likely to be higher than would be seen in an SIMD computer. This overhead means that grain size must be sufficiently large to exploit the parallelism efficiently.
       • multithreading processor
       • general purpose processor
   • instruction set architecture (ISA)
     • The ISA serves as the boundary between the software and hardware. A realization of an ISA, is a CPU. In general, an ISA defines the supported data types, the registers, the hardware support for managing main memory fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA.
     • Instructions  Opcodes, Addressing Modes, Data Types  Instruction Types and Formats  Registers, Condition Codes  Memory  Address space, Addressability, Alignment  Virtual memory management  Call, Interrupt/Exception Handling  Access Control, Priority/Privilege  I/O: memory-mapped vs. instr.  Task/thread Management  Power and Thermal Management  Multi-threading support, Multiprocessor support
     • set of architectures by CPU instructions type
       • RISC
         • (Reduced Instruction Set Computer): set of architectures with simpler instructions
         • tablets/phones
       • CISC
         •  complex instruction set computer. is a computer in which single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step operations or addressing modes within single instructions. 
         • laptops/desktops
     • properties
       • Class of ISA
         • Nearly all ISAs today are classified as general-purpose register architectures, where the operands are either registers or memory locations. The 80x86 has 16 general-purpose registers and 16 that can hold floatingpoint data, while MIPS has 32 general-purpose and 32 floating-point registers. The two popular versions of this class are register-memory ISAs, such as the 80x86, which can access memory as part of many instructions, and load-store ISAs, such as ARM and MIPS, which can access memory only with load or store instructions. All recent ISAs are load-store.
       • Memory addressing
         • Virtually all desktop and server computers, including the 80x86, ARM, and MIPS, use byte addressing to access memory operands. Some architectures, like ARM and MIPS, require that objects must be aligned. An access to an object of size s bytes at byte address A is aligned if A mod s = 0.  The 80x86 does not require alignment, but accesses are generally faster if operands are aligned.
       • Addressing modes
         • In addition to specifying registers and constant operands, addressing modes specify the address of a memory object. MIPS addressing modes are Register, Immediate (for constants), and Displacement, where a constant offset is added to a register to form the memory address. The 80x86 supports those three plus three variations of displacement: no register (absolute), two registers (based indexed with displacement), and two registers where one register is multiplied by the size of the operand in bytes (based with scaled index and displacement). It has more like the last three, minus the displacement field, plus register indirect, indexed, and based with scaled index. ARM has the three MIPS addressing modes plus PC-relative addressing, the sum of two registers, and the sum of two registers where one register is multiplied by the size of the operand in bytes. It also has autoincrement and autodecrement addressing, where the calculated address replaces the contents of one of the registers used in forming the address.
       • Types and sizes of operands
         • Like most ISAs, 80x86, ARM, and MIPS support operand sizes of 8-bit (ASCII character), 16-bit (Unicode character or half word), 32-bit (integer or word), 64-bit (double word or long integer), and IEEE 754 floating point in 32-bit (single precision) and 64-bit (double precision). The 80x86 also supports 80-bit floating point (extended double precision).
       • Operations
         • The general categories of operations are data transfer, arithmetic logical, control (discussed next), and floating point. MIPS is a simple and easy-to-pipeline instruction set architecture, and it is representative of the RISC architectures being used in 2011. The 80x86 has a much richer and larger set of operations.
       • Encoding an ISA
         • There are two basic choices on encoding: fixed length and variable length. All ARM and MIPS instructions are 32 bits long, which simplifies instruction decoding. The 80x86 encoding is variable length, ranging from 1 to 18 bytes. Variablelength instructions can take less space than fixed-length instructions, so a program compiled for the 80x86 is usually smaller than the same program compiled for MIPS. Note that choices mentioned above will affect how the instructions are encoded into a binary representation. For example, the number of registers and the number of addressing modes both have a significant impact on the size of instructions, as the register field and addressing mode field can appear many times in a single instruction. (Note that ARM and MIPS later offered extensions to offer 16-bit length instructions so as to reduce program size, called Thumb or Thumb-2 and MIPS16, respectively.)
       • Data types
         • Definition: Representation of information for which there are instructions that operate on the representation:   Integer, floating point, character, binary, decimal, BCD    Doubly linked list, queue, string, bit vector, stack 
       • Registers
         • special-purpose
           • The special-purpose registers include things like the program counter and stack pointer, as well as other registers with a specific function. these registers available only in kernel mode.
         • Program Status Word
           • This register holds various miscellaneous bits that are needed by the CPU. The most important bits are the condition codes. These bits are set on every ALU cycle and reflect the status of the result of the most recent operation.
         • general-purpose
           •  the general-purpose registers are there to hold key local variables and intermediate results of calculations. Their main function is to provide rapid access to heavily used data (basically, avoiding memory accesses). These  registers visible to user programs by user mode
       • instructions
         • Control flow instructions
           • Change the sequence of instructions that are executed. Virtually all ISAs, including these three, support conditional branches, unconditional jumps, procedure calls, and returns. All three use PC-relative addressing, where the branch address is specified by an address field that is added to the PC. There are some small differences. MIPS conditional branches (BE, BNE, etc.) test the contents of registers, while the 80x86 and ARM branches test condition code bits set as side effects of arithmetic/logic operations. The ARM and MIPS procedure call places the return address in a register, while the 80x86 call (CALLF) places the return address on a stack in memory. 
         • Operate instructions
           • - Process data: arithmetic and logical operations  - Fetch operands, compute result, store result  - Implicit sequential control flow 
         • Data movement instructions
           • - Move data between memory, registers, I/O devices  - Implicit sequential control flow 
       • Privilege modes
         • User
         • supervisor/kernel
       • Virtual memory
     • implementation of ISA
       • ARM
       • AMD
       • INTEL
       • MIPS
     • Classifying ISA
       • The way operands may be accessed directly from memory or may need to be first loaded into temporary storage, depending on the class of architecture and choice of specific instruction. 
       • stack architecture
         •  The operands  are implicitly on the top of the stack
       • accumulator architecture
         • one operand is implicitly the accumulator. 
       • general-purpose register architectures (GPR)
         •  have only explicit operands—either registers or memory locations.
         • classes of GPR computers.
           • register-memory architecture
             •  can access memory as part of any instruction. operands stored in:   Register-memory result stored in: register 
           • load-store architecture
             • can access memory only with load and store instructions.  operands stored in:   Register-Register result stored in: register  
           • memory-memory architecture
             •  not found in computers shipping today, keeps all operands in memory 
     • consists of three primary components
       • the operations
       • the data types
       • the addressing modes
     • Instruction Fetch architecture
       • the way cpu fetch instruction to pipeline
       • single inst/cycle
         • fetch one instruction per cycle to pipeline
         • non superscalar
       • multiple inst/cycle
         • fetch multiple instruction per cycle to pipeline and attempt to execute more than 1 instruction-per-cycle
         • VLIM
           • compiler decides what inst can be exe in parallel 
         • superscalar
           • hardware detects dependencies between instructions that are fetched in the same cycle
   • memory
     • cache
       • its frequently used data. Its highest or first level of the memory hierarchy which provide locality and fast access. Since the principle of locality applies at many levels, and taking advantage of locality to improve performance is popular, the term cache is now applied whenever buffering is employed to reuse commonly occurring items. Examples include file caches, name caches, and so on.
       • cache maping hierarchy
         • Its the way how main memory copy will be placed to cache
         • direct mapped
           • the placement policy for each entry in main memory can go in just one place in the cache
         • fully associative.
           • the placement policy is free to choose any entry in the cache to hold the copy
         • set associative.
           • the placement policy a compromise in which each entry in main memory can go to any one of N places in the cache
       • block (line run)
         • cache consists of fixed-size collection of data containing the requested word which is called as block or line run
       • cache address translations
         • Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses:
         • Physically indexed, physically tagged (PIPT)
           • caches use the physical address for both the index and the tag. 
         • Virtually indexed, virtually tagged (VIVT)
           • caches use the virtual address for both the index and the tag.
         • Virtually indexed, physically tagged (VIPT)
           • caches use the virtual address for the index and the physical address in the tag.
         • Physically indexed, virtually tagged (PIVT)
           • caches are often claimed in literature to be useless and non-existing.
       • Cache strategies
         • Other than mapping mechanism, caches also need a range of strategies that specify what should happen in the case of certain events. In case of (set-) associative caches, the cache must determine which cache block is to be replaced by a new block entering the cache.
         • First-In First Out (FIFO)
         • Least Recently Used (LRU)
     • registers
   • arifmetic logical unit (ALU)
   • Cores
     • core classification
       • core its amount processors per microprocessor
       • mullticore
         • A multi-core processor is a computer processor integrated circuit with two or more separate processing units
         • symmetric shared-memory multiprocessors (SMPs)
         • distributed shared memory (DSM).
       • singlecore
         • A multi-core processor is a computer processor integrated circuit with one processing unit
   • Interrupts
     • External and internal interrupts are initiated from signals that occur in the hardware of the CPU whereas Software interrupts occur from the instructions.
     • software Interrupts
       • The interrupt that is caused by any internal system of the computer system is known as a software interrupt. It is initiated by executing an instruction. It can be used by the programmer to initiate an interrupt at the desired point in the program.
       • Normal Interrupt
         • The interrupts that are caused by software instructions are called normal software interrupts.
       • Exception
         • Unplanned interrupts which are produced during the execution of some program are called exceptions, such as division by zero.
     • External int
       • This kind of interrupt are asynchronous. It arises due to external call from I/O devices. For e.g. I/O devices requesting transfer of data, power failure, etc. These are also called “interrupt”. 
     • Internal int
       • This kind of interrupt are synchronous. It arises due to illegal and erroneous use of an instruction or data. For e.g. stack overflow, division by zero, invalid opcode, etc. These are also called  trap/system call /exception 
       • Hardware Interrupts
         • When the signal for the processor is from an external device or hardware then this interrupts is known as hardware interrupt.
         • Maskable Interrupt
           • The hardware interrupts which can be delayed when a much high priority interrupt has occurred at the same time.
         • Non Maskable Interrupt
           • The hardware interrupts which cannot be delayed and should be processed by the processor immediately.Non Maskable Interrupt
     • class of int
       • vector int
         • A vectored interrupt is where the CPU actually knows the address of the Interrupt Service Routine in advance. All it needs is that the interrupting device sends its unique vector via a data bus and through its I/O interface to the CPU. The CPU takes this vector, checks an interrupt table in memory, and then carries out the correct ISR for that device. So the vectored interrupt allows the CPU to be able to know what ISR to carry out in software (memory).
       • non vector
         • A non-vectored interrupt is where the interrupting device never sends an interrupt vector. An interrupt is received by the CPU, and it jumps the program counter to a fixed address in hardware. This is literally a hard coded ISR which is device agnostic. MIPS uses this via it’s syscall instruction, which is the same instruction you use regardless what device, if it is an external event notifier (e.g. keyboard input), a completion signal (e.g. print completion), a clock interrupt to tell the CPU to allocate control to a different device, or an abnormal event indicator (e.g. power failure). The CPU crucially does not know which device caused the interrupt without polling each I/O interface in a loop and checking the status register of each I/O interface to find the one with status “interrupt created”.  
   • controll unit (CU)
     • Hardwired CU
       • It is implemented circuit based in the hardware
     • Microprogrammed CU
       • It is implemented by using programming approach. A sequence of micro operations is carried out by executing a program consisting of micro-instructions. In this organization any modifications or changes can be done by updating the micro program in the control memory by the programmer.

3. implementation of a computer

   • microarchitecture (or organization)
     •  The term microarchitecture includes the high-level aspects of a computer’s design, such as the memory system, the memory interconnect, and the design of the internal processor or CPU (central processing unit—where arithmetic, logic, branching, and data transfer are implemented). 
     • Implementation of the ISA under specific design constraints and goals  Anything done in hardware without exposure to software  Pipelining  In-order versus out-of-order instruction execution  Memory access scheduling policy  Speculative execution  Superscalar processing (multiple instruction issue?)  Clock gating  Caching? Levels, size, associativity, replacement policy  Prefetching?  Voltage/frequency scaling?  Error correction?
     • class of cycle
       • Multi-cycle machines
         •  Control signals needed in the next cycle can be generated in the current cycle  Latency of control processing can be overlapped with latency of datapath operation (more parallelism)  Instruction processing broken into multiple cycles/stages  State updates can be made during an instruction’s execution  Architectural state updates made only at the end of an instruction’s execution  Advantage over single-cycle: The slowest “stage” determines cycle time
       • Single-cycle machines
         •  Control signals are generated in the same clock cycle as the one during which data signals are operated on  Everything related to an instruction happens in one clock cycle (serialized processing)  Each instruction takes a single clock cycle  All state updates made at the end of an instruction’s execution  Big disadvantage: The slowest instruction determines cycle time  long clock cycle time
     • instruction processing engine
       • Datapath
         •  Consists of hardware elements that deal with and transform data signals  functional units that operate on data  hardware structures (e.g. wires and muxes) that enable the flow of data into the functional units and registers  storage units that store data (e.g., registers)
       • Control logic
         • Consists of hardware elements that determine control signals, i.e., signals that specify what the datapath elements should do to the data
         • microcoded/microprogrammed
           • Control signals stored in a memory structure 
           • Microinstruction
             •  control signals that control the datapath (26 of them) and help determine the next state (9 of them) 
           • control store
             • Each microinstruction is stored in a unique location in the control store (a special memory structure) 
             • architecture
               • Horizontal Microcode
                 • A single control store provides the control signals
               • Vertical Microcode
                 • Two-level control store: the first specifies abstract operations 
                 • Microinstruction
                   • Control signals associated with the current state 
             • type of signall
               • Three types of control signals
               • Datapath Control Signals
                 • Control signals that control the operation of the datapath
               • Control Store Signals
                 • Control signals (microinstructions) stored in control store to be used in pipelined datapath (can be propagated to stages later than decode) 
               • Stall Signals
                 • Ensure the pipeline operates correctly in the presence of dependencies
           • Microsequencer
             •  determines the address of the next microinstruction (i.e., next state) 
         • Hardwired/combinational
           • Control signals generated by combinational logic 
     • levels of instructions
       • Millicode
         •  a level above traditional microcode. Its ISA-level subroutines that can be called by the microcontroller to handle complicated operations and system functions
         • microcode
           • instruction that generate Control signals and state of cycle processing. basically its a programming of control signals
           • Nanocode
             • a level below traditional microcode. microprogrammed control for sub-systems (e.g., a complicated floating-point module) that acts as a slave in a microcontrolled datapath
   • hardware
     • Hardware refers to the specifics of a computer, including the detailed logic design and the packaging technology of the computer. Often a line of computers contains computers with identical instruction set architectures and nearly identical organizations, but they differ in the detailed hardware implementation. 
     • Dataflow model
       •  An instruction is fetched and executed in data flow order  - i.e., when its operands are ready  - i.e., there is no instruction pointer  - Instruction ordering specified by data flow dependence - Each instruction specifies “who” should receive the result  - An instruction can “fire” whenever all operands are received
   • ISA
     • von Neumann model
       • sequential execution

4. memory

   • type of memory
     • main memory
       • volatile
         • in contrast to non-volatile memory, is computer memory that requires power to maintain the stored information; it retains its contents while powered on but when the power is interrupted, the stored data is quickly lost.
         • RAM
           • Random Access Memory. It is also called as read write memory or the main memory or the primary memory.The programs and data that the CPU requires during execution of a program are stored in this memory.It is a volatile memory as the data loses when the power is turned off.RAM is further classified into two types- SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory).
           • DRAM
             • dynamic random access memory. The dynamic nature of the circuits in DRAM requires data to be written back after being read—hence the difference between the access time and the cycle time as well as the need to refresh
           • SRAM
             • static random access memory. don’t need to refresh, so the access time is very close to the cycle time.
       • non-volatile
         •  is a type of computer memory that can retrieve stored information even after having been power cycled. In contrast, volatile memory needs constant power in order to retain data.
         • Flash memory
           •  is a type of EEPROM (Electronically Erasable Programmable Read-Only Memory), which is normally read-only but can be erased. The other key property of Flash memory is that it holds it contents without any power. 
         • ROM
           • Read Only Memory. Stores crucial information essential to operate the system,  used for storing firmware such as BIOS, like the program essential to boot the computer.It is not volatile.Always retains its data.Used in embedded systems or where the programming needs no change.Used in calculators and peripheral devices.ROM is further classified into 4 types- ROM, PROM, EPROM, and EEPROM.
           • PROM
             • (Programmable read-only memory) – It can be programmed by user. Once programmed, the data and instructions in it cannot be changed.
           • EPROM
             • EPROM (Erasable Programmable read only memory) – It can be reprogrammed. To erase data from it, expose it to ultra violet light. To reprogram it, erase all the previous data.
           • EEPROM
             • (Electrically erasable programmable read only memory) – The data can be erased by applying electric field, no need of ultra violet light. We can erase only portions of the chip.
     • secondary storage devices
       • SSD/HDD drives
   • units of memory
     • block (or line)
       • consists of multiple words
     • word
       • piece of data
   • technics to exploit memory
     • virtual memory
       • Virtual memory is a system where all physical memory is controlled by the operating system. The address space broken into fixed-size blocks, called pages. pages are mapped from the virtual address space into physical address space via a page table. OS and processes working with these pages of memory
       • page table
         •  Its list of pages with adresses. The protection restrictions are included in each page table entry. The protection restrictions might determine whether a user process can read this page, whether a user process can write to this page, and whether code can be executed from this page. In addition, a process can neither read nor write a page if it is not in the page table. Since only the OS can update the page table, the paging mechanism provides total access protection.
         • pages
           • block in virtual memory with fixed-size.
         • types of page tables
           • Inverted page tables (IPT)
           • Multilevel page tables
           • Virtualized page tables
           • Nested page tables
     • Cache
       • its frequently used data. Its highest or first level of the memory hierarchy which provide locality and fast access. Since the principle of locality applies at many levels, and taking advantage of locality to improve performance is popular, the term cache is now applied whenever buffering is employed to reuse commonly occurring items. Examples include file caches, name caches, and so on.
     • Data buffer (Memory buffer/buffer)
       • is a region of a physical memory storage used to temporarily store data while it is being moved from one place to another. typically use RAM to store temporary data.
       • Buffers are typically used when there is a difference between the rate at which data is received and the rate at which it can be processed, or in the case that these rates are variable (network, I/O). For example different I/O devices where either input are faster then output. A buffer often adjusts timing by implementing a queue (or FIFO) algorithm in memory, simultaneously writing data into the queue at one rate and reading it at another rate. 
       • Buffers can increase application performance by allowing synchronous operations such as file reads or writes to complete quickly instead of blocking while waiting for hardware interrupts to access a physical disk subsystem; instead, an operating system can immediately return a successful result from an API call, allowing an application to continue processing while the kernel completes the disk operation in the background. 
     • physical memory
       • descriptor table
         • segments
           • block in virtual memory with variable-size.
   • Shared Memory cache
     • common used cache between different processors
     • Uniform Memory Access (UMA)
     • Non-Uniform Memory Access (NUMA)
     • Cache Only Memory Architecture (COMA)

5. security

   • secrutity between programs and processes. Its service purpose of safe switch between different cotext of programs.
   • mode of execution
     • user mode
       • user process.
     • kernel mode (or supervisor)
       • operating system process.
   • processor state
     •  the processor state that a user process can use but not write. This state includes a user/supervisor mode bit, an exception enable/disable bit, and memory protection information. Users are prevented from writing this state because the operating system cannot control user processes if users can give themselves supervisor privileges, disable exceptions, or change memory protection.
   • system call
     • Provide mechanisms whereby the processor can go from user mode to supervisor mode and vice versa. The first direction is typically accomplished by a system call, implemented as a special instruction that transfers control to a dedicated location in supervisor code space. The PC is saved from the point of the system call, and the processor is placed in supervisor mode. The return to user mode is like a subroutine return that restores the previous user/supervisor mode. (e.g., open, close, read, write, seek on “files”) 
   • limit memory between processes
     • Provide mechanisms to limit memory accesses to protect the memory state of a process without having to swap the process to disk on a context switch.
   • virtual memory
     • Virtual memory is a system where all physical memory is controlled by the operating system. The address space broken into fixed-size blocks, called pages. pages are mapped from the virtual address space into physical address space via a page table. OS and processes working with these pages of memory

6. I/O Organisation

   • Interrupt Initiated I/O
     • he interface determines that the peripheral is ready for data transfer, it generates an interrupt. After receiving the interrupt signal, the CPU stops the task which it is processing and service the I/O transfer and then returns back to its previous processing task.
   • Programmed I/O
     • the result of I/O instructions written in computer program. Each data item transfer is initiated by the instruction in the program.  Transferring data under programmed I/O requires constant monitoring of the peripherals by the CPU.
   • Direct Memory Access (DMA)
     • peripheral device manage the memory buses directly. the interface transfer data to and from the memory through memory bus.
     • Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards and sound cards etc. 

7. data transmission

   • Modes Of Transmission data
     • Simplex
       • A simplex line carries information in one direction only. In this mode receiver cannot communicate with the sender to indicate the occurrence of errors that means only sender can send data but receiver cannot. For example: Radio and Television Broadcasting.
     • Half Duplex
       • In half duplex mode, system is capable of transmitting data in both directions but data can be transmitted in one direction only at a time. A pair of wires is needed for this mode. For example: Walkie - Talkie.
     • Full Duplex
       • In this mode data can be send and received in both directions simultaneously. In this four wire link is used.For example: Video Calling, Audio calling etc. 
   • protocols
     • set of ruls to transfer data.
     • Character Oriented Protocol
       • It is based on the binary code of character set. The code is mostly used in ASCII. It includes upper case and lower case letters, numerals and variety of special symbols. The characters that control the transmission is called communication control characters.
     • Bit Oriented Protocol
       • It does not use characters in its control field and is independent of any code. It allows the transmission of serial bit stream of any length without the implication of character boundaries.

8. Input/Output

   • Input/Output Processor (IOP)
     • The IOP is similar to CPU except that it handles only the details of I/O processing. The IOP can fetch and execute its own instructions. These IOP instructions are designed to manage I/O transfers only.
     • also have names as: channel, peripheral processor, I/O processor, I/O controller, or DMA controller.
   • I/O Channels
     • A channel is an independent hardware component that co-ordinate all I/O to a set of controllers. Computer systems that use I/O channel have special hardware components that handle all I/O operations.
     • Multiplexer
       • The Multiplexer channel can be connected to a number of slow and medium speed devices. It is capable of operating number of I/O devices simultaneously.
     • Selector
       • This channel can handle only one I/O operation at a time and is used to control one high speed device at a time.
     • Block-Multiplexer
       • It combines the features of both multiplexer and selector channels.

9. bus

   • its core set hardware which connects all devaces together and allow interconnection between each other 
   • Asynchronous Bus
     • does not have a master clock. All devices can interact with other asynchronously by communication protocols.
   • Synchronous Bus
     • has a line driven by a crystal oscillator. The signal on this line consists of a square wave with a frequency generally between 5 and 133 MHz. All bus activities take an integral number of these cycles, called bus cycles

10. classification pc by the way exe instructions

    • Dataflow Model
      •  An instruction is fetched and executed in data flow order  i.e., when its operands are ready  i.e., there is no instruction pointer  Instruction ordering specified by data flow dependence  Each instruction specifies “who” should receive the result  An instruction can “fire” whenever all operands are received  Potentially many instructions can execute at the same time  Inherently more parallel 
      •  Data-driven, parallel execution  An instruction is executed when all its operand values are available (data flow) 
    • Von Neumann model:
      •  An instruction is fetched and executed in control flow order  As specified by the instruction pointer  Sequential unless explicit control flow instruction
      •  Control-driven, sequential execution  An instruction is executed when the IP points to it  IP automatically changes sequentially (except for control flow instructions)
      • All major instruction set architectures today use this model  x86, ARM, MIPS, SPARC, Alpha, POWER

11. buffer

    • entity that control communication of two different devices in different rate.
    • temporary storage to store some temporary storage. example: buffer of many pending instructions, a.k.a. reservation stations

12. PARALLEL COMPUTER ARCHITECTURES

    • on chip parallelism
      • parallelism within one CPU by instruction level parallelism and thread level parallelism
    • corprocessor
      • its specialized subprocessor that being under control of main processor
    • multiprocessor
      • A parallel computer in which all the CPUs share a common memory is called a multiprocessor
    • A multicomputer
      •  design for a parallel architecture is one in which each CPU has its own private memory, accessible only to itself and not to any other CPU. Such a design is called a multicomputer, or sometimes a distributed memory system
    • A grid
      • set of multicomputers 

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