Fichas
Digital and Embedded System
Fichas del conjunto (5)
- 1Princeton ArchitectureCISC
simple & economic
single data bus to fetch data
common memory space
one bus creates bottlenecks
execution time is high
instruction and data treated the same - 2Harvard ArchitectureRISC
Complex & expensive
separate buses for memory
instructions and data fetched simultaneously (pipe lining)
free data memory cant be used for instruction (vice versa) - 3Power on Reset PORwill hold device in reset while conditions are met
prevents device running software until min VDD is met - 4Power up Timer PWRTprovides nomial 72 millisecond delay after a power on reset
it operates on a dedicated internal RC - 5Oscillator Start Up Timer OSTProvides a 1024 oscillator cycle delay after PWRT delay
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- Descripción
- Engineering Fichas sobre Digital and Embedded System, creado por Caoimhe McCreanor el 08/05/2018.
- Creado por
- Caoimhe McCreanor
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