Flashcards
Timing Flashcards
Cards in this deck (11)
- 1What are 4 methods of reducing propagation delays in a digital logic circuit to achieve positive slack.1. Change optimization settings. Generating more logic in parallel
or 'pipelining' (dividing computation across multiple clock cycles).
2. Use a larger and/or faster device (or silicon process). Larger gates means less resistance.
3. Modify the design so that there is less combinational logic in the paths that are not meeting timing.
4. Relax the design constraints by reducing the required clock rate. - 2Which circuit paths need to be analyzed for Static Timing Analysis?Those that start at a clock input
and end at a D input of a flip-flop
(input and output ports may also need to be considered for
timing analysis depending on the design). - 3Define Closing Timing.The process of iterating a design until all paths have positive slack.
- 4Define Metastability and how can it be avoided.In a synchronous digital system, if the D input to a flip-flop is near the threshold voltage when the clock transitions the flip-flip may not be able to detect the correct value to output. This can result in incorrect operation of the circuit.
This condition can be avoided by ensuring set up and hold times are met before and after active clock transitions. - 5What are the 5 timing components used in Static Timing Analysis.1. Minimum Clock Period (T): 1/fclk
2. Maximum Propagation Delay (tpd): delay from a change at an input to a change at an output.
3. Maximum Clock-to-Output Delay (tco): Propagation delay from a clock input to flip-flop output.
4. Set Up Time (tsu): Time in which input to a flip-flop must be held constant BEFORE a clock input.
tsu(available) = T(min) - tpd(max) - tco(max)
tsu(available) must be > than tsu(required) to avoid metastability.
5. Hold Time (th): Time in which input to a flip-flop must be held constant AFTER a clock input.
th(available) = tpd(min) + tco(min) - T(max) - 6Name 3 common sources of timing variations that are typically factored into timing analysis.Process, Voltage, & Temperature
- 7What is a Synopsys Time Constraint (SDC)?A standard file format used to specify timing information for a digital design.
The constraints are specified as TCL commands. - 8Clock Domain Crossing: When asynchronous clocks are used how do we analysis timing stability?Consider failures resulting from metastability as a random process (MTBF)
- 9Clock Domain Crossing: What is the best way to increase the MTBF?Increase positive slack
- 10Clock Domain Crossing: How does multi-flop synchronization for single bit data increase MTBF?There is probability that while sampling the input of FF1, that its output may go into metastable state.
But during the one clock cycle period, the FF1 output may settle to some stable value. - 11Clock Domain Crossing: How to synchronize multi-bit data?Four-Phase Handshake:
Multi-flop synchronized req & ack control signals are used. The
data is held steady until the handshake is complete.
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- Digital Design Flashcards on Timing Flashcards, created by Bryce Reid on 19/05/2026.
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- Bryce Reid
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- Created by Bryce Reid · May 16, 2026
- Copied by Bryce Reid · May 19, 2026
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